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| this is information on a product in full production. november 2016 docid14395 rev 15 1/125 stm8af526x/8x/ax stm8af6269/8x/ax automotive 8-bit mcu, with up to 128 kbyte flash, data eeprom, 10-bit adc, timers, lin, can, usart, spi, i2c, 3 to 5.5 v datasheet - production data features ? aec-q10x qualified ? core ?max f cpu : 24 mhz ? advanced stm8a core with harvard architecture and 3-stage pipeline ? average 1.6 cycles/inst ruction resulting in 10 mips at 16 mhz f cpu for industry standard benchmark ? memories ? program memory: 32 to 128 kbyte flash program; data retention 20 years at 55 c ? data memory: up to 2 kbyte true data eeprom; endurance 300 kcycle ? ram: 6 kbyte ? clock management ? low-power crystal re sonator oscillator with external clock input ? internal, user-trimmable 16 mhz rc and low-power 128 khz rc oscillators ? clock security system with clock monitor ? reset and supply management ? wait/auto-wakeup/halt low-power modes with user definable clock gating ? low consumption power-on and power- down reset ? interrupt management ? nested interrupt controller with 32 vectors ? up to 37 external interrupts on 5 vectors ? timers ? 2 general purpose 16-bit timers with up to 3 capcom channels each (ic, oc, pwm) ? advanced control timer: 16-bit, 4 capcom channels, 3 complementary outputs, dead- time insertion and flex ible synchronization ? 8-bit ar basic timer with 8-bit prescaler ? auto-wakeup timer ? window and independent watchdog timers ? i/os ? up to 68 user pins (11 high sink i/os) ? highly robust i/o design, immune against current injection ? communication interfaces ? high speed 1 mbit/s can 2.0b interface ? usart with clock output for synchronous operation - lin master mode ? linuart lin 2.2 compliant, master/slave modes with automatic resynchronization ? spi interface up to 10 mbit/s or f master /2 ?i 2 c interface up to 400 kbit/s ? analog to digital converter (adc) ? 10-bit resolution, 2 lsb tue, 1 lsb linearity and up to 16 multiplexed channels ? operating temperature up to 150 c ? qualification conforms to aec-q100 grade 0 table 1. device summary (1) 1. in the order code, ?f? applies to devices with flash program memory and data eeprom. ?f? is replaced by ?p? for devices with fastrom (see table 2 , table 3 and figure 60 ). reference part number stm8af526x/8x/ax (with can) stm8af5268, STM8AF5269, stm8af5286, stm8af5288, stm8af5289, stm8af528a, stm8af52a6, stm8af52a8, stm8af52a9, stm8af52aa stm8af6269/8x/ax stm8af6269, stm8af6286, stm8af6288, stm8af6289, stm8af628a, stm8af62a6, stm8af62a8, stm8af62a9, stm8af62aa vfqfp32 5x5 mm lqfp32 7x7 mm lqfp48 7x7 mm lqfp64 10x10 mm lqfp80 14x14 mm www.st.com
contents stm8af526x/8x/ax stm8af6269/8x/ax 2/125 docid14395 rev 15 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 product line-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 stm8a central processing unit (cpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1.1 architecture and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1.2 addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1.3 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2 single wire interface module (swim) and debug module (dm) . . . . . . . . 15 5.2.1 swim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2.2 debug module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.4 flash program and data eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.4.1 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.4.2 write protection (wp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.4.3 protection of user boot code (ubc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.4.4 read-out protection (rop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.5 clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.5.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.5.2 16 mhz high-speed internal rc oscillator (hsi) . . . . . . . . . . . . . . . . . . 17 5.5.3 128 khz low-speed internal rc oscillator (lsi) . . . . . . . . . . . . . . . . . . . 18 5.5.4 24 mhz high-speed external crystal oscillator (hse) . . . . . . . . . . . . . . . 18 5.5.5 external clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.5.6 clock security system (css) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.6 low-power operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.7 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.7.1 watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.7.2 auto-wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.7.3 beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 docid14395 rev 15 3/125 stm8af526x/8x/ax stm8af6269/8x/ax contents 4 5.7.4 advanced control and general purpose timers . . . . . . . . . . . . . . . . . . . 20 5.7.5 basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.8 analog to digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.9 communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.9.1 universal synchronous/asynchronous receiver transmitter (usart) . . 22 5.9.2 universal asynchronous rece iver/transmitter with lin support (linuart) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.9.3 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.9.4 inter integrated circuit (i 2 c) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.9.5 controller area network interface (becan) . . . . . . . . . . . . . . . . . . . . . . 26 5.10 input/output specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6 pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.1 package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.2 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7 memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.2 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8 interrupt table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9 option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 10 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 10.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 10.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10.3.1 vcap external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 10.3.2 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 10.3.3 external clock sources and timing characteristics . . . . . . . . . . . . . . . . . 68 10.3.4 internal clock sources and timing characte ristics . . . . . . . . . . . . . . . . . 70 contents stm8af526x/8x/ax stm8af6269/8x/ax 4/125 docid14395 rev 15 10.3.5 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 10.3.6 i/o port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 10.3.7 reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 10.3.8 tim 1, 2, 3, and 4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . 80 10.3.9 spi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 10.3.10 i 2 c interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 10.3.11 10-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 10.3.12 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 11 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 11.1 lqfp80 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 11.2 lqfp64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 11.3 lqfp48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 11.4 lqfp32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 11.5 vfqfpn32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 11.6 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 11.6.1 reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 11.6.2 selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 110 12 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 13 stm8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 13.1 emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . .112 13.1.1 stice key features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 13.2 software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 13.2.1 stm8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 13.2.2 c and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 13.3 programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 docid14395 rev 15 5/125 stm8af526x/8x/ax stm8af6269/8x/ax list of tables 6 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. stm8af526x/8x/ax product line-up with can . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 3. stm8af6269/8x/ax product line-up without can . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 4. peripheral clock gating bits (clk_pckenr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 5. peripheral clock gating bits (clk_pckenr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 6. advanced control and general purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 7. tim4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 8. adc naming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 9. communication peripheral naming correspondence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 10. legend/abbreviation for the pin description table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 11. stm8af526x/8x/ax and stm8af6269/8x/ax pin desc ription . . . . . . . . . . . . . . . . . . . . . . 34 table 12. memory model 128k. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 13. i/o port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 14. general hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 15. cpu/swim/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 16. temporary memory unprotection registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 17. stm8a interrupt table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 18. option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 19. option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 20. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 21. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 22. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 23. operating lifetime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 24. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 25. operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 26. total current consumption in run, wait and slow mode. general conditions for v dd apply, t a = -40 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 27. total current consumption in halt an d active-halt modes. general conditions for v dd applied. t a = -40 c to 55 c unless otherwise stated . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 28. oscillator current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 29. programming current consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 table 30. typical peripheral current consumption v dd = 5.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 31. hse external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 32. hse oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 33. hsi oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 34. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 35. flash program memory/data eeprom memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 36. flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 37. data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 38. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 39. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 40. tim 1, 2, 3, and 4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 41. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 42. i 2 c characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 43. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 44. adc accuracy for v dda = 5 v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 45. ems data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 46. emi data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 list of tables stm8af526x/8x/ax stm8af6269/8x/ax 6/125 docid14395 rev 15 table 47. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 48. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 49. lqfp80 - 80-pin, 14 x 14 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 50. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 51. lqfp48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 52. lqfp32 - 32-pin, 7 x 7 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 53. vfqfpn32 - 32-pin, 5 x 5 mm, 0.5 mm pitch very thin profile fine pitch quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 54. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 55. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 docid14395 rev 15 7/125 stm8af526x/8x/ax stm8af6269/8x/ax list of figures 8 list of figures figure 1. stm8af526x/8x/ax and stm8af6269/8x/ax block diagram . . . . . . . . . . . . . . . . . . . . . . 12 figure 2. flash memory organization of stm8a products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 3. lqfp 80-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 4. lqfp 64-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 5. lqfp 48-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 6. stm8af62xx lqfp/vfqfpn 32-pin pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 7. stm8af52x6 vfqfpn32 32-pin pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 8. register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 9. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 10. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 11. fcpumax versus vdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 12. external capacitor c ext . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 13. typ. i dd(run)hse vs. v dd @f cpu = 16 mhz, peripherals = on . . . . . . . . . . . . . . . . . . . . . . 67 figure 14. typ. i dd(run)hse vs. f cpu @v dd = 5.0 v, peripherals = on . . . . . . . . . . . . . . . . . . . . . . . 67 figure 15. typ. i dd(run)hsi vs. v dd @f cpu = 16 mhz, peripherals = off . . . . . . . . . . . . . . . . . . . . . . 67 figure 16. typ. i dd(wfi)hse vs. v dd @f cpu = 16 mhz, peripherals = on . . . . . . . . . . . . . . . . . . . . . . 67 figure 17. typ. i dd(wfi)hse vs. f cpu @v dd = 5.0 v, peripherals = on . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 18. typ. i dd(wfi)hsi vs. v dd @f cpu = 16 mhz, peripherals = off . . . . . . . . . . . . . . . . . . . . . . 67 figure 19. hse external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 20. hse oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 21. typical hsi frequency vs v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 22. typical lsi frequency vs v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 23. typical v il and v ih vs v dd @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 24. typical pull-up resistance r pu vs v dd @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . 75 figure 25. typical pull-up current i pu vs v dd @ four temperatures (1) . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 26. typ. v ol @ v dd = 3.3 v (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 27. typ. v ol @ v dd = 5.0 v (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 28. typ. v ol @ v dd = 3.3 v (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 29. typ. v ol @ v dd = 5.0 v (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 30. typ. v ol @ v dd = 3.3 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 31. typ. v ol @ v dd = 5.0 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 32. typ. v dd - v oh @ v dd = 3.3 v (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 33. typ. v dd - v oh @ v dd = 5.0 v (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 34. typ. v dd - v oh @ v dd = 3.3 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 35. typ. v dd - v oh @ v dd = 5.0 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 36. typical nrst v il and v ih vs v dd @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 37. typical nrst pull-up resistance r pu vs v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 38. typical nrst pull-up current i pu vs v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 39. recommended reset pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 40. spi timing diagram in slave mode and with cpha = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 41. spi timing diagram in slave mode and with cpha = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 42. spi timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 43. typical application with adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 44. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 45. lqfp80 - 80-pin, 14 x 14 mm low-profile quad fl at package outline . . . . . . . . . . . . . . . . . 90 figure 46. lqfp80 - 80-pin, 14 x 14 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 47. lqfp80 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 list of figures stm8af526x/8x/ax stm8af6269/8x/ax 8/125 docid14395 rev 15 figure 48. lqfp64 - 64-pin, 10 x 10 mm low-profile quad fl at package outline . . . . . . . . . . . . . . . . . 94 figure 49. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 50. lqfp64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 51. lqfp48 - 48-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 97 figure 52. lqfp48 - 48-pin, 7 x 7 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 53. lqfp48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 54. lqfp32 - 32-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 101 figure 55. lqfp32 - 32-pin, 7 x 7 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 56. lqfp32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 57. vfqfpn32 - 32-pin, 5x5 mm, 0.5 mm pitch very thin profile fine pitch quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 58. vfqfpn32 - 32-pin, 5 x 5 mm, 0.5 mm pitch very thin profile fine pitch quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 59. vfqfpn32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 60. stm8af526x/8x/ax and stm8af6269/8x/ax ordering information scheme 1 . . . . . . . . . 111 docid14395 rev 15 9/125 stm8af526x/8x/ax stm8af6269/8x/ax introduction 114 1 introduction this datasheet refers to the stm8af526x/8 x/ax and stm8af6269/8x/ax products with 32 to 128 kbyte of program memory. in the order code, the letter ?f ? refers to product versions with flash and data eeprom and ?p? to product versions with fastrom. the iden tifiers ?f? and ?p? do not coexist in a given order code. the datasheet contains the description of family features, pinout, electr ical characteristics, mechanical data and ordering information. ? for complete information on the stm8a microcontroller memory, registers and peripherals, please refer to stm8s series and stm8af series 8-bit microcontrollers reference manual (rm0016). ? for information on programming, erasing and protection of the internal flash memory please refer to the stm8s and stm8a flash programming manual (pm0051). ? for information on the debug and swim (s ingle wire interface module) refer to the stm8 swim communication protocol and debug module user manual (um0470). ? for information on the stm8 core, please refer to the stm8 cpu programming manual (pm0044). description stm8af526x/8x/ax stm8af6269/8x/ax 10/125 docid14395 rev 15 2 description the stm8af526x/8x/ax and stm8af6269/8x/ ax automotive 8-bit microcontrollers described in this datasheet offer from 32 kbyte to 128 kbyte of non volatile memory and integrated true data eeprom. they are referr ed to as high density stm8a devices in stm8s series and stm8af series 8-bit microcontrollers reference manual (rm0016). the stm8af52 series features a can interface. all devices of the stm8a product line provi de the following benefits: reduced system cost, performance and robustness, short deve lopment cycles, and product longevity. the system cost is reduced thanks to an integrated true data eeprom for up to 300 k write/erase cycles and a high system integrat ion level with internal clock oscillators, wtachdog, and brown-out reset. device performance is ensured by 20 mips at 24 mhz cpu clock frequency and enhanced characteristics which include robust i/o, independent watchdogs (with a separate clock source), and a clock security system. short development cycles ar e guaranteed due to application scalability across a common family product architecture with compatible pinout, memory map, and modular peripherals. full documentation is offered with a wide choice of development tools. product longevity is ensured in the stm8a fam ily thanks to their advanced core which is made in a state-of-the art technology for automotive applications with 3.3 v to 5.5 v operating supply. all stm8a and st7 microcontrollers are supported by the same tools including stvd/stvp development environment, the stice emulator and a low-cost, third party in- circuit debugging tool. docid14395 rev 15 11/125 stm8af526x/8x/ax stm8af6269/8x/ax product line-up 114 3 product line-up .. . table 2. stm8af526x/8x/ax product line-up with can order code package high density flash program memory (bytes) ram (bytes) data eeprom (bytes) 10-bit a/d chan. timers (ic/oc/pwm) serial interfaces i/0 wakeup pins stm8af/p52aa lqfp80 (14x14) 128 k 6 k 2 k 16 1x8-bit: tim4 3x16-bit: tim1, tim2, tim3 (9/9/9) can, lin(uart), spi, usart, i2c 68/37 stm8af/p528a 64 k stm8af/p52a9 lqfp64 (10x10) 128 k 52/36 stm8af/p5289 64 k stm8af/p5269 32 k 1 k stm8af/p52a8 lqfp48 (7x7) 128 k 2 k 10 38/35 stm8af/p5288 64 k stm8af/p5268 32 k 1k stm8af/p5286 vfqfpn32 (5x5) 64 k 2k 6 1x8-bit: tim4 3x16-bit: tim1, tim2, tim3 (8/8/8) can, lin(uart), i2c 25/24 stm8af/p52a6 128 k table 3. stm8af6269/8x/ax product line-up without can order code package high density flash program memory (bytes) ram (bytes) data eeprom (bytes) 10-bit a/d chan. timers (ic/oc/pwm) serial interfaces i/0 wakeup pins stm8af/p62aa lqfp80 (14x14) 128 k 6 k 2 k 16 1x8-bit: tim4 3x16-bit: tim1, tim2, tim3 (9/9/9) lin(uart), spi, usart, i2c 68/37 stm8af/p628a 64 k stm8af/p62a9 lqfp64 (10x10) 128 k 52/36 stm8af/p6289 64 k 2 k stm8af/p6269 32 k 1 k stm8af/p62a8 lqfp48 (7x7) 128 k 2 k 10 38/35 stm8af/p6288 64 k stm8af/p6286 lqfp32 (7x7) 7 1x8-bit: tim4 3x16-bit: tim1, tim2, tim3 (8/8/8) lin(uart), spi, i2c 25/23 stm8af/p62a6 vfqfpn32 (5x5) 128 k block diagram stm8af526x/8x/ax stm8af6269/8x/ax 12/125 docid14395 rev 15 4 block diagram figure 1. stm8af526x/8x/ax and stm8af6269/8x/ax block diagram ; 7 $ / 0 + ] 5 & l q w 0 + ] 5 & l q w n + ] 6 7 0 $ f r u h ' h e x j 6 : , 0 6 3 , 8 6 $ 5 7 e l w $ 5 w l p h u 7 , 0 5 h v h w e o r f n 5 h v h w 3 2 5 % 2 5 & o r f n f r q w u r o o h u ' h w h f w r u & o r f n w r s h u l s k h u d o v d q g f r u h 0 e l w v 0 d v w h u v o d y h d x w r p d w l f u h v \ q f k u r q l ] d w l r q $ g g u h v v d q g g d w d e x v : l q g r z : ' * 8 s w r . e \ w h k l j k g h q v l w \ s u r j u d p ) o d v k 8 s w r . e \ w h 8 s w r . e \ w h 5 $ 0 e l w $ ' & 5 h v h w . e l w v 6 l q j o h z l u h g h e x j l q w h u i d f h e l w d g y d q f h g f r q w u r o w l p h u 7 , 0 e l w j h q h u d o s x u s r v h w l p h u v 7 , 0 7 , 0 g d w d ( ( 3 5 2 0 , q g h s h q g h q w : ' * & $ 3 & 2 0 f k d q q h o v 8 s w r 8 s w r f k d q q h o v , & % r r w 5 2 0 0 6 9 $ : 8 w l p h u / , 1 8 $ 5 7 / , 1 p d v w h u 6 3 , h p x o e h & $ 1 0 e l w v docid14395 rev 15 13/125 stm8af526x/8x/ax stm8af6269/8x/ax block diagram 114 1. legend: adc: analog-to-digital converter becan: controller area network bor: brownout reset i2c: inter-integrated circuit multimaster interface iwdg: independent window watchdog linuart: local interconnect network unive rsal asynchronous receiver transmitter por: power on reset spi: serial peripheral interface swim: single wire interface module usart: universal synchronous as ynchronous receiver transmitter window wdg: window watchdog product overview stm8af526x/8x/ax stm8af6269/8x/ax 14/125 docid14395 rev 15 5 product overview this section is intended to desc ribe the family features that are actually implemented in the products covered by this datasheet. for more detailed information on each feature please refer to stm8s series and stm8af series 8-bit microcontrollers reference manual (rm0016). 5.1 stm8a central processing unit (cpu) the 8-bit stm8a core is a modern cisc core and has been designed for code efficiency and performance. it contains 21 internal r egisters (six directly addressable in each execution context), 20 addressing modes including indexed indirect and relative addressing and 80 instructions. 5.1.1 architecture and registers ? harvard architecture ? 3-stage pipeline ? 32-bit wide program memory bus with single cycle fetching for most instructions ? x and y 16-bit index registers, enabling indexed addressing modes with or without offset and read-modify-write type data manipulations ? 8-bit accumulator ? 24-bit program counter with 16-mbyte linear memory space ? 16-bit stack pointer with access to a 64 kbyte stack ? 8-bit condition code register with seven cond ition flags for the result of the last instruction. 5.1.2 addressing ? 20 addressing modes ? indexed indirect addressing mode for look-up tables located anywhere in the address space ? stack pointer relative addressing mode for efficient implementation of local variables and parameter passing 5.1.3 instruction set ? 80 instructions with 2-byte average instruction size ? standard data movement and logic/arithmetic functions ? 8-bit by 8-bit multiplication ? 16-bit by 8-bit and 16-bit by 16-bit division ? bit manipulation ? data transfer between stack and accumu lator (push/pop) with direct stack access ? data transfer using the x and y registers or direct memory-to-memory transfers docid14395 rev 15 15/125 stm8af526x/8x/ax stm8af6269/8x/ax product overview 114 5.2 single wire interface module (swim) and debug module (dm) 5.2.1 swim the single wire interface module, swim, together with an integrated debug module, permits non-intrusive, real-time in-circuit debugging and fast memory programming. the interface can be activated in all device operation modes and can be connected to a running device (hot plugging).the maximum data transmission speed is 145 bytes/ms. 5.2.2 debug module the non-intrusive debugging module features a performance close to a full-flavored emulator. besides memory and peripheral operation, cpu operation can also be monitored in real-time by means of shadow registers. ? r/w of ram and peripheral registers in real-time ? r/w for all resources when th e application is stopped ? breakpoints on all program-m emory instructions (software breakpoints), except the interrupt vector table ? two advanced breakpoints and 23 predefined breakpoint configurations 5.3 interrupt controller ? nested interrupts with three software priority levels ? 24 interrupt vectors with hardware priority ? five vectors for external interrupts (up to 37 depending on the package) ? trap and reset interrupts 5.4 flash program and data eeprom ? 32 kbytes to 128 kbytes of high dens ity single voltage flash program memory ? up to 2 kbytes true (n ot emulated) data eeprom ? read while write: writing in the data memory is possible while executing code in the flash program memory. the whole flash program memo ry and data eeprom are fa ctory programmed with 0x00. 5.4.1 architecture ? the memory is organized in blocks of 128 bytes each ? read granularity: 1 word = 4 bytes ? write/erase granularity: 1 word (4 bytes) or 1 block (128 bytes) in parallel ? writing, erasing, word and block management is handled automatically by the memory interface. product overview stm8af526x/8x/ax stm8af6269/8x/ax 16/125 docid14395 rev 15 5.4.2 write protection (wp) write protection in application mode is intended to avoid unintentional overwriting of the memory. the write protection can be removed te mporarily by executin g a specific sequence in the user software. 5.4.3 protection of us er boot code (ubc) if the user chooses to update the flash program memory using a specific boot code to perform in application programming (iap), this boot code needs to be protected against unwanted modification. in the stm8a a memory area of up to 128 kbyt es can be protected from overwriting at user option level. other than the standard write prot ection, the ubc protection can exclusively be modified via the debug interface, the user software cannot modify the ubc protection status. the ubc memory area contains the reset and in terrupt vectors and its size can be adjusted in increments of 512 bytes by programming the ubc and nubc option bytes (see section 9: option bytes on page 54 ). figure 2. flash memory organization of stm8a products 5.4.4 read-out protection (rop) the stm8a provides a read-out protection of the code and data memory which can be activated by an option byte setting (s ee the rop option byte in section 10). the read-out protection prevents reading and writing flash program memory, data memory and option bytes via the debug module and swim in terface. this protection is active in all device operation modes. any attempt to remove the protection by overwriting the rop option byte triggers a global erase of the program and data memory. 8 % & d u h d ) o d v k s u r j u d p p h p r u \ d u h d ' d w d p h p r u \ d u h d 5 h p d l q v z u l w h s u r w h f w h g g x u l q j , $ 3 ' d w d ( ( 3 5 2 0 p h p r u \ : u l w h d f f h v v s r v v l e o h i r u , $ 3 2 s w l r q e \ w h v 3 u r j u d p p d e o h d u h d i u r p . e \ w h i l u v w w z r s d j h v x s w r s u r j u d p p h p r u \ h q g p d [ l p x p . e \ w h ) o d v k s u r j u d p p h p r u \ 0 6 9 docid14395 rev 15 17/125 stm8af526x/8x/ax stm8af6269/8x/ax product overview 114 the rop circuit may provide a temporary acce ss for debugging or failure analysis. the temporary read access is protected by a user defined, 8-byte keyword stored in the option byte area. this keyword must be entered via the swim interface to temporarily unlock the device. if desired, the temporary unlock mechanism can be permanently disabled by the user through opt6/nopt6 option bytes. 5.5 clock controller the clock controller distributes the system clock coming from different os cillators to the core and the peripherals. it also manages clock gating for low-power modes and ensures clock robustness. 5.5.1 features ? clock sources ? 16 mhz high-speed internal rc oscillator (hsi) ? 128 khz low-speed internal rc (lsi) ? 1-24 mhz high-speed external crystal (hse) ? up to 24 mhz high-speed user-external clock (hse user-ext) ? reset : after reset the microcontroller restarts by default with an internal 2-mhz clock (16 mhz/8). the clock source and speed can be changed by the application program as soon as the code execution starts. ? safe clock switching : clock sources can be changed safely on the fly in run mode through a configuration register. the clock signal is not switched until the new clock source is ready. the design guarantees glitch-free switching. ? clock management : to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. ? wakeup : in case the device wakes up from low-power modes, the internal rc oscillator (16 mhz/8) is used for quick star tup. after a stabilization time, the device switches to the clock source that was selected before halt mode was entered. ? clock security system (css) : the css permits monitoring of external clock sources and automatic switching to the internal rc (16 mhz/8) in case of a clock failure. ? configurable main clock output (cco) : this feature permits to output a clock signal for use by the application. 5.5.2 16 mhz high-speed intern al rc oscillator (hsi) ? default clock after reset 2 mhz (16 mhz/8) ? fast wakeup time user trimming the register clk_hsitrimr with two trimming bits plus one additional bit for the sign permits frequency tuning by the application program. the adjustment range covers all possible frequency variations versus supply voltage and temperature. this trimming does not change the initial production setting. product overview stm8af526x/8x/ax stm8af6269/8x/ax 18/125 docid14395 rev 15 5.5.3 128 khz low-speed intern al rc oscillator (lsi) the frequency of this clock is 128 khz and it is independent from the main clock. it drives the independent watchdog or the awu wakeup timer. in systems which do not need independent clock sources for the watchdog counters, the 128 khz signal can be used as the system cloc k. this configuration has to be enabled by setting an option byte (opt3/opt3n, bit lsi_en). 5.5.4 24 mhz high-speed exter nal crystal oscillator (hse) the external high-speed crystal oscillator can be selected to deliver the main clock in normal run mode. it operates with qu artz crystals and ceramic resonators. ? frequency range: 1 mhz to 24 mhz ? crystal oscillation mode: preferred fundamental ? i/os: standard i/o pins mult iplexed with oscin, oscout 5.5.5 external clock input an external clock signal can be applied to the oscin input pin of the crystal oscillator. the frequency range is 0 to 24 mhz. 5.5.6 clock security system (css) the clock security system protects against a syst em stall in case of an external crystal clock failure. in case of a clock failure an interrupt is generated and the high-speed internal clock (hsi) is automatically selected with a fr equency of 2 mhz (16 mhz/8). table 4. peripheral clock gating bits (clk_pckenr1) control bit peripheral pcken17 tim1 pcken16 tim3 pcken15 tim2 pcken14 tim4 pcken13 linuart pcken12 usart pcken11 spi pcken10 i 2 c docid14395 rev 15 19/125 stm8af526x/8x/ax stm8af6269/8x/ax product overview 114 5.6 low-power operating modes for efficient power management , the application can be put in one of four different low- power modes. users can configure each mode to obtain the best compromise between lowest power consumption, fastest start- up time and available wakeup sources. ? wait mode in this mode, the cpu is stopped but perip herals are kept running. the wakeup is performed by an internal or external interr upt or reset. ? active-halt mode with regulator on in this mode, the cpu and peripheral clocks are stopped. an internal wakeup is generated at programmable intervals by th e auto wake up unit (awu). the main voltage regulator is kept powered on, so current consumption is higher than in active- halt mode with regulator off, but the wakeup time is faster. wakeup is triggered by the internal awu interrupt, ex ternal interrupt or reset. ? active-halt mode with regulator off this mode is the same as active-halt with re gulator on, except that the main voltage regulator is powered off, so the wake up time is slower. ? halt mode cpu and peripheral clocks ar e stopped, the main voltage regulator is powered off. wakeup is triggered by external event or reset. in all modes the cpu and peri pherals remain perm anently powered on, the system clock is applied only to selected modules. the ram content is preserved and the brown-out reset circuit remains activated. table 5. peripheral clock gating bits (clk_pckenr2) control bit peripheral pcken27 can pcken26 reserved pcken25 reserved pcken24 reserved pcken23 adc pcken22 awu pcken21 reserved pcken20 reserved product overview stm8af526x/8x/ax stm8af6269/8x/ax 20/125 docid14395 rev 15 5.7 timers 5.7.1 watchdog timers the watchdog system is based on two independent timers providing maximum security to the applications. the watchdog timer activity is controlled by the application program or option bytes. once the watchdog is activated, it cannot be disabled by the user program without going through reset. window watchdog timer the window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by un expected logical conditions, which cause the application program to abandon its normal sequence. the window function can be used to trim the watchdog behavior to match the application timing perfectly. the application software must refresh the counter before time-out and during a limited time window. if the counter is refreshed outside this ti me window, a reset is issued. independent watchdog timer the independent watchdog peripheral can be us ed to resolve malfunctions due to hardware or software failures. it is clocked by the 128 khz lsi internal rc cloc k source, and thus stays active even in case of a cpu clock failure. if the hardware watchdog feature is enabled through the device option bits, the watchdog is automatically enabled at power-on, and generates a reset unless the key register is written by software before the counter reaches the end of count. 5.7.2 auto-wakeup counter this counter is used to cyclically wakeup the device in active-halt mode. it can be clocked by the internal 128 khz in ternal low-frequency rc o scillator or external clock. lsi clock can be internally connected to ti m3 input capture channel 1 for calibration. 5.7.3 beeper this function generates a rectangular signal in the range of 1, 2 or 4 khz which can be output on a pin. this is useful when audi ble sounds without interference need to be generated for use in the application. 5.7.4 advanced control and general purpose timers stm8a devices described in this datasheet, cont ain up to three 16-bit advanced control and general purpose timers providing nine capcom channels in total. a capcom channel can be used either as input compare, output compare or pwm channel. these timers are named tim1, tim2 and tim3. docid14395 rev 15 21/125 stm8af526x/8x/ax stm8af6269/8x/ax product overview 114 tim1 - advanced control timer this is a high-end timer designed for a wi de range of control applications. with its complementary outputs, dead-tim e control and center-aligned pw m capability, the field of applications is extended to motor c ontrol, lighting and bridge driver. ? 16-bit up, down and up/down ar (auto-rel oad) counter with 16-bit fractional prescaler. ? four independent capcom channels configurab le as input capture, output compare, pwm generation (edge and center aligned mode) and single pulse mode output ? trigger module which allows th e interaction of tim1 with other on-chip peripherals. in the present implementation it is possibl e to trigger the adc upon a timer event. ? external trigger to change the timer behavior depending on external signals ? break input to force the timer outputs into a defined state ? three complementary outputs with adjustable dead time ? interrupt sources: 4 x input capture/output compare, 1 x overflow/update, 1 x break tim2, tim3 - 16-bit general purpose timers ? 16-bit auto-reload up-counter ? 15-bit prescaler adjustable to fixed power of two ratios 1?32768 ? timers with three or two individually configurable capcom channels ? interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update 5.7.5 basic timer the typical usage of this timer (tim4) is the generation of a clock tick. ? 8-bit auto-reload, adjustable prescaler ratio to any power of two from 1 to 128 ? clock source: master clock ? interrupt source: 1 x overflow/update table 6. advanced control and general purpose timers timer counter width counter type prescaler factor channels inverted outputs repetition counter trigger unit external trigger break input tim1 16-bit up/down 1 to 65536 4 3 yes yes yes yes tim2 16-bit up 2 n n = 0 to 15 3 none no no no no tim3 16-bit up 2 n n = 0 to 15 2 none no no no no table 7. tim4 timer counter width counter type prescaler factor channels inverted outputs repetition counter trigger unit external trigger break input tim4 8-bit up 2 n n = 0 to 7 0 none no no no no product overview stm8af526x/8x/ax stm8af6269/8x/ax 22/125 docid14395 rev 15 5.8 analog to digital converter (adc) the stm8a products described in this datasheet contain a 10-bit successive approximation adc with up to 16 multiplexed input channels, depending on the package. the adc name differs between the datasheet and the stm8a/s reference manual (see table 8 ). adc features ? 10-bit resolution ? single and continuous conversion modes ? programmable prescaler: f master divided by 2 to 18 ? conversion trigger on timer events, and external events ? interrupt generation at end of conversion ? selectable alignment of 10-bit dat a in 2 x 8 bit result registers ? shadow registers for data consistency ? adc input range: v ssa v in v dda ? schmitt-trigger on analog inputs can be disabled to reduce power consumption 5.9 communication interfaces the following sections give a brief overview of the communication peripheral. some peripheral names differ between the datasheet and stm8s series and stm8af series 8-bit microcontrollers reference manual (see table 9 ). 5.9.1 universal synchronous/asynchr onous receiver tran smitter (usart) the devices covered by this datasheet contain one usart interface. the usart can operate in standard sci mode (serial communication interface, asynchronous) or in spi emulation mode. it is equipped with a 16 bit fr actional prescaler. it features lin master support. table 8. adc naming peripheral name in datasheet peripheral name in reference manual (rm0016) adc adc2 table 9. communication peripheral naming correspondence peripheral name in datasheet peripheral name in reference manual (rm0016) usart uart1 linuart uart3 docid14395 rev 15 23/125 stm8af526x/8x/ax stm8af6269/8x/ax product overview 114 detailed feature list: ? full duplex, asynchronous communications ? nrz standard format (mark/space) ? high-precision baud rate generator system ? common programmable transmit and receive baud rates up to f master /16 ? programmable data word length (8 or 9 bits) ? configurable stop bits: support for 1 or 2 stop bits ? lin master mode: ? lin break and delimiter generation ? lin break and delimiter detection with separate flag and interrupt source for readback checking. ? transmitter clock output for synchronous communication ? separate enable bits for transmitter and receiver ? transfer detection flags: ? receive buffer full ? transmit buffer empty ? end of transmission flags ? parity control: ? transmits parity bit ? checks parity of received data byte ? four error detection flags: ? overrun error ? noise error ? frame error ? parity error ? six interrupt sources with flags: ? transmit data register empty ? transmission complete ? receive data register full ? idle line received ? parity error ? lin break and delimiter detection ? two interrupt vectors: ? transmitter interrupt ? receiver interrupt ? reduced power consumption mode ? wakeup from mute mode (by idle line detection or address mark detection) ? two receiver wakeup modes: ? address bit (msb) ? idle line product overview stm8af526x/8x/ax stm8af6269/8x/ax 24/125 docid14395 rev 15 5.9.2 universal asynch ronous receiver/transmitter with lin support (linuart) the devices covered by this datasheet contain one linuart interface. the interface is available on all the supported packages. the linuart is an asynchronous serial communication interface which supports ext ensive lin functions tailored for lin slave applications. in lin mode it is compliant to the lin standards rev 1.2 to rev 2.2. detailed feature list: lin mode master mode ? lin break and delimiter generation ? lin break and delimiter detection with separate flag and interrupt source for read back checking. slave mode ? autonomous header handling ? one single interrupt per valid header ? mute mode to filter responses ? identifier parity error checking ? lin automatic resynchronizat ion, allowing operation with internal rc oscillator (hsi) clock source ? break detection at any time, even during a byte reception ? header errors detection: ? delimiter too short ? synch field error ? deviation error (if automatic resynchronization is enabled) ? framing error in synch field or identifier field ? header time-out uart mode ? full duplex, asynchronous communications - nrz standard format (mark/space) ? high-precision baud rate generator ? a common programmable transmit and receive baud rates up to f master /16 ? programmable data word length (8 or 9 bits) ? 1 or 2 stop bits ? parity control ? separate enable bits for transmitter and receiver ? error detection flags ? reduced power consumption mode ? multi-processor communication - enter mute mode if address match does not occur ? wakeup from mute mode (by idle line detection or address mark detection) ? two receiver wakeup modes: ? address bit (msb) ? idle line docid14395 rev 15 25/125 stm8af526x/8x/ax stm8af6269/8x/ax product overview 114 5.9.3 serial peripheral interface (spi) the devices covered by this datasheet contain one spi. the spi is available on all the supported packages. ? maximum speed: 10 mbit/s or f master /2 for master, 8 mbit/s or f master /2 for slave ? full duplex synchronous transfers ? simplex synchronous transfers on two lines with a possible bidirectional data line ? master or slave operation - selectable by hardware or software ? crc calculation ? 1 byte tx and rx buffer ? slave mode/master mode management by hardware or software for both master and slave ? programmable clock polarity and phase ? programmable data order with msb-first or lsb-first shifting ? dedicated transmission and receptio n flags with inte rrupt capability ? spi bus busy status flag ? hardware crc feature for reliable communication: ? crc value can be transmitted as last byte in tx mode ? crc error checking for last received byte 5.9.4 inter integrated circuit (i 2 c) interface the devices covered by this datasheet contain one i 2 c interface. the inte rface is available on all the supported packages. ? i 2 c master features: ? clock generation ? start and stop generation ? i 2 c slave features: ? programmable i 2 c address detection ? stop bit detection ? generation and detection of 7-bit/10-bit addressing and general call ? supports different communication speeds: ? standard speed (up to 100 khz), ? fast speed (up to 400 khz) ? status flags: ? transmitter/receiver mode flag ? end-of-byte transmission flag ?i 2 c busy flag ? error flags: ? arbitration lost condition for master mode ? acknowledgement failure after address/data transmission ? detection of misplaced start or stop condition ? overrun/underrun if clock stretching is disabled product overview stm8af526x/8x/ax stm8af6269/8x/ax 26/125 docid14395 rev 15 ? interrupt: ? successful address/data communication ? error condition ? wakeup from halt ? wakeup from halt on address detection in slave mode 5.9.5 controller area network interface (becan) the becan controller (basic enhanced can), interfaces the can network and supports the can protocol version 2.0a and b. it is equipp ed with a receive fifo and a very versatile filter bank. together with a filter match index, this allows a very efficient message handling in today?s car network architectures. the cp u is significantly unloaded. the maximum transmission speed is 1 mbit/s. transmission ? three transmit mailboxes ? configurable transmit priority by identifier or order request reception ? 11- and 29-bit id ? 1 receive fifo (3 messages deep) ? software-efficient mailbox mapping at a unique address space ? fmi (filter match index) stored with message for quick message association ? configurable fifo overrun ? time stamp on sof reception ? 6 filter banks, 2 x 32 bytes (scalable to 4 x 16-bit) each, enabling various masking configurations, such as 12 filters for 29 -bit id or 48 filters for 11-bit id. ? filtering modes (mixable): ? mask mode permitting id range filtering ? id list mode interrupt management ? maskable interrupt ? software-efficient mailbox mapping at a unique address space docid14395 rev 15 27/125 stm8af526x/8x/ax stm8af6269/8x/ax product overview 114 5.10 input/output specifications the product features four i/o types: ? standard i/o 2 mhz ? fast i/o up to 10 mhz ? high sink 8 ma, 2 mhz ? true open drain (i 2 c interface) to decrease emi (electromagnetic interference), high sink i/os have a limited maximum slew rate. the rise and fall times ar e similar to those of standard i/os. the analog inputs are equipped with a low leakage analog switch. additionally, the schmitt- trigger input stage on the analog i/os can be disabled in order to reduce the device standby consumption. stm8a i/os are designed to withstand current in jection. for a negative injection current of 4 ma, the resulting leakage current in the adja cent input does not exceed 1 a. thanks to this feature, external protec tion diodes against current injection are no longer required. caution: in stm8af5286uc device, the following i/o ports are not automatically configured by hardware: pa3, pa4, pa5, pa6, pf4, pb6, pb7, pe0, pe1, pe2, pe3, pe6, pe7. as a consequence, they must be put into one of the following configurations by software: - configured as input with internal pull-up/down resistor, - configured as output push-pull low. pinouts and pin description stm8af526x/8x/ax stm8af6269/8x/ax 28/125 docid14395 rev 15 6 pinouts and pin description 6.1 package pinouts figure 3. lqfp 80-pin pinout 1. the can interface is only av ailable on stm8af52xx product lines. 2. (hs) stands for high sink capability. pd4 (hs)/tim2_ch1/beep 2 1 3 4 5 6 7 8 10 9 12 14 16 18 20 11 15 13 17 19 25 26 28 27 30 32 34 36 38 29 33 31 35 37 39 57 58 56 55 54 53 52 51 49 50 47 45 43 41 48 44 46 42 60 59 61 62 63 64 66 68 65 67 69 70 71 72 74 73 75 76 77 78 79 80 pi4 pi3 pi2 pi1 pc4 (hs)/tim1_ch4 pc3 (hs)/tim1_ch3 pc2 (hs)/tim1_ch2 pc1 (hs)/tim1_ch1 pg6 pg5 pi5 pi0 pg4 pg3 pg2 pc7/spi_miso v ssio_2 v ddio_1 tim2_ch3/pa3 usart_rx/pa4 usart_tx/pa5 ain12/pf4 v ssio_1 v ss vcap v dd usart_ck/pa6 (hs) ph0 ( hs) ph1 ph2 ph3 ain15/pf7 ain14/pf6 ain13/pf5 nrst oscin/pa1 oscout/pa2 ain5/pb5 ain4/pb4 ain1/pb1 ain0/pb0 ain8/pe7 v ref- ain10/pf0 ain7/pb7 ain6/pb6 tim1_etr/ph4 tim1_ch3n/ph5 tim1_ch2n/ph6 40 ain9/pe6 21 22 24 23 ain11/pf3 v ref+ v dda v ssa pd0 (hs)/tim3_ch2 pe2/i 2c_sda pe3/tim1_bkin pe4 pg7 pd7/tli pd6/linuart_rx pd5/linuart_tx pi7 pi6 pd2 (hs)/tim3_ch1 pd1 (hs)/swim pc5/spi_sck pc6/spi_mosi pg0/can_tx (1) pg1/can_rx (1) pe0/clk_cco pd3 (hs)/tim2_ch2 ain3/pb3 ain2/pb2 pc0/adc_etr pe5/spi_nss tim1_ch1n/ph7 v ddio_2 pe1/i2c_scl docid14395 rev 15 29/125 stm8af526x/8x/ax stm8af6269/8x/a x pinouts and pin description 114 figure 4. lqfp 64-pin pinout 1. the can interface is only av ailable on stm8af52xx product lines. 2. hs stands for hi gh sink capability. v ref- ain10/pf0 ain7/pb7 ain6/pb6 ain5/pb5 ain4/pb4 tim1_etr/ain3/pb3 tim1_ch3n/ain2/pb2 tim1_ch2n/ain1/pb1 tim1_ch1n/ain0/pb0 ain8/pe7 ain9/pe6 ain11/pf3 v ref+ v dda v ssa 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v ss vcap v dd v ddio_1 tim2_ch3/pa3 usart_rx/pa4 usart_tx/pa5 usart_ck/pa6 ain15/pf7 ain14/pf6 ain13/pf5 ain12/pf4 nrst oscin/pa1 oscout/pa2 v ssio_1 pg1/can_rx (1) pg0/can_tx (1) pc7/spi_miso pc6/spi_mosi v ddio_2 v ssio_2 pc5/spi_sck pc4 (hs)/tim1_ch4 pc3 (hs)/tim1_ch3 pc2 (hs)/tim1_ch2 pc1 (hs)/tim1_ch1 pe5/spi_nss pi0 pg4 pg3 pg2 pd3 (hs)/tim2_ch2/adc_etr pd2 (hs)/tim3_ch1 pd1 (hs)/swim pd0 (hs)/tim3_ch2 pe0/clk_cco pe1/i2c_scl pe2/i2c_sda pe3/tim1_bkin pe4 pg7 pg6 pg5 pd7/tli pd6/linuart_rx pd5/linuart_tx pd4 (hs)/tim2_ch1/ beep pinouts and pin description stm8af526x/8x/ax stm8af6269/8x/ax 30/125 docid14395 rev 15 figure 5. lqfp 48-pin pinout 1. the can interface is only av ailable on stm8af52xx product lines. 2. hs stands for hi gh sink capability. 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 48 47 46 45 usart_ck/pa6 ain8/pe7 pc1 (hs)/tim1_ch1 pe5/spi_nss pg1/can_rx ain9/pe6 pd3 (hs)/tim2_ch2/adc_etr pd2 (hs)/tim3_ch1 pe0/clk_cco pe1/i 2 c_scl pe2/i 2 c_sda pe3/tim1_bkin pd7/tli pd6/linuart_rx pd5/linuart_tx pd4 (hs)/tim2_ch1/beep pd1 (hs)/swim pd0 (hs)/tim3_ch2 v ssio_2 pc5/spi_sck pc4 (hs)/tim1_ch4 pc3 (hs)/tim1_ch3 pc2 (hs)/tim1_ch2 pg0/can_tx pc7/spi_miso pc6/spi_mosi v ddio_2 ain7/pb7 ain6/pb6 ain5/pb5 ain4/pb4 tim1_etr/ain3/pb3 tim1_ch3n/ain2/pb2 tim1_ch2n/ain1/pb1 tim1_ch1n/ain0/pb0 v dda v ssa v ss vcap v dd v ddio_1 tim2_ch3/pa3 usart_rx/pa4 usart_tx/pa5 nrst oscin/pa1 oscout/pa2 v ssio_1 docid14395 rev 15 31/125 stm8af526x/8x/ax stm8af6269/8x/a x pinouts and pin description 114 figure 6. stm8af62xx lqfp/vfqfpn 32-pin pinout 1. hs stands for hi gh sink capability. i2c_scl/ain4/pb4 tim1_etr/ain3/pb3 tim1_ch3n/ain2/pb2 tim1_ch2n/ain1/pb1 tim1_ch1n/ain0/pb0 v dda v ssa i2c_sda/ain5/pb5 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9101112 13 14 15 16 1 2 3 4 5 6 7 8 vcap v dd v ddio ain12/pf4 nrst oscin/pa1 oscout/pa2 v ss pc3 (hs)/tim1_ch3 pc2 (hs)/tim1_ch2 pc1 (hs)/tim1_ch1 pe5/spi_nss pc7/spi_miso pc6/spi_mosi pc5/spi_sck pc4 (hs)/tim1_ch4 pd3 (hs)/tim2_ch2/adc_etr pd2 (hs)/tim3_ch1/tim2_ch3 pd1 (hs)/swim pd0 (hs)/tim3_ch2/clk_cco/tim1_brk pd7/tli pd6/linuart_rx pd5/linuart_tx pd4 (hs)/tim2_ch1/beep pinouts and pin description stm8af526x/8x/ax stm8af6269/8x/ax 32/125 docid14395 rev 15 figure 7. stm8af52x6 vfqfpn32 32-pin pinout 1. the following i/o ports are not automatically configured by hardware: pa3, pa4, pa5, pa6, pf4, pb6, pb7, pe0, pe1, pe2, pe3, pe6, pe7. as a consequence, they must be put into one of the following configurations by software: - configured as input with internal pull-up/down resistor, - configured as output push-pull low. 2. hs stands for hi gh sink capability. 3 ' 7 / , 1 % - * / 6 " 3 5 @ 3 9 ' / , 1 8 $ 5 7 b 7 ; 3 ' + 6 7 , 0 b & + % ( ( 3 3 ' + 6 7 , 0 b & + $ ' & b ( 7 5 3 ' + 6 7 , 0 b & + 7 , 0 b & + 3 ' + 6 6 : , 0 3 ' + 6 7 , 0 b & + & / . b & & 2 7 , 0 b % 5 . 3 * & $ 1 b 5 ; 3 ( 3 & + 6 7 , 0 b & + 3 & + 6 7 , 0 b & + 3 & + 6 7 , 0 b & + 3 & + 6 7 , 0 b & + 3 & 3 * & $ 1 b 7 ; 3 $ 9 ' ' , 2 9 ' ' 9 & $ 3 9 6 6 2 6 & 2 8 7 3 $ 2 6 & , 1 3 $ 1 5 6 7 9 ' ' $ 9 6 6 $ , & b 6 ' $ $ , 1 3 % , & b 6 & / $ , 1 3 % 7 , 0 b ( 7 5 $ , 1 3 % 7 , 0 b & + 1 $ , 1 3 % 7 , 0 b & + 1 $ , 1 3 % 7 , 0 b & + 1 $ , 1 3 % 0 6 9 docid14395 rev 15 33/125 stm8af526x/8x/ax stm8af6269/8x/a x pinouts and pin description 114 table 10. legend/abbreviation for the pin description table type i= input, o = output, s = power supply level input cm = cmos (standard for all i/os) output hs = high sink (8 ma) output speed o1 = standard (up to 2 mhz) o2 = fast (up to 10 mhz) o3 = fast/slow programmability with slow as default state after reset o4 = fast/slow programmability with fast as default state after reset port and control configuration input float = floating, wpu = weak pull-up output t = true open drain, od = open drain, pp = push pull reset state bold x (pin state after reset release). unless otherwise specified, the pin state is the same during the reset phase (i.e. ?under reset?) and after internal reset release (i.e. at reset state). pinouts and pin description stm8af526x/8x/ax stm8af6269/8x/ax 34/125 docid14395 rev 15 table 11. stm8af526x/8x/ax and stm8af6269/8x/ax pin description pin number pin name type input output main function (after reset) default alternate function alternate function after remap [option bit] lqfp80 lqfp64 lqfp48 stm8af62xx lqfp32/vfqfpn32 stm8af52x6 vfqfpn32 floating wpu ext. interrupt high sink speed od pp 111 1 1 nrst i/o- x -- - - - reset - 222 2 2 pa1/oscin (1) i/o x x- - o1 x x port a1 resonator/ crystal in - 3 3 3 3 3 pa2/oscout i/o x xx - o1 x x port a2 resonator/ crystal out - 444 - - v ssio_1 s - - - - - - - i/o ground - 555 4 4 v ss s - - - - - - - digital ground - 6 6 6 5 5 vcap s - - - - - - - 1.8 v regulator capacitor - 777 6 6 v dd s - - - - - - - digital power supply - 888 7 7 v ddio_1 s - - - - - - - i/o power supply - 999 - - pa3/tim2_ch3i/o x xx - o1 x x port a3 timer 2 - channel 3 tim3_ch1 [afr1] 10 10 10 - - pa4/usart_rx i/o x xx - o3 x x port a4 usart receive - 11 11 11 - - pa5/usart_tx i/o x xx - o3 x x port a5 usart transmit - 12 12 12 - 8 pa6/usart_ck (2) i/o x xx - o3 x x port a6 usart synchro nous clock - 13---- ph0 i/oxx-hso3xx port h0 -- 14---- ph1 i/o x x-hso3 x x port h1 -- 15---- ph2 i/o x x- - o1 x x port h2 -- 16---- ph3 i/o x x- - o1 x x port h3 -- 17 13 - - - pf7/ain15 i/o x x- - o1 x x port f7 analog input 15 - 18 14 - - - pf6/ain14 i/o x x- - o1 x x port f6 analog input 14 - 19 15 - - - pf5/ain13 i/o x x- - o1 x x port f5 analog input 13 - 20 16 - 8 - pf4/ain12 i/o x x- - o1 x x port f4 analog input 12 - 21 17 - - - pf3/ain11 i/o x x- - o1 x x port f3 analog input 11 - docid14395 rev 15 35/125 stm8af526x/8x/ax stm8af6269/8x/a x pinouts and pin description 114 22 18 - - - v ref+ s---- - - - adc positive reference voltage - 23 19 13 9 9 v dda s - - - - - - - analog power supply - 24 20 14 10 10 v ssa s - - - - - - - analog ground - 25 21 - - - v ref- s---- - - - adc negative reference voltage - 26 22 - - - pf0/ain10 i/o x x- - o1 x x port f0 analog input 10 - 27 23 15 - - pb7/ain7 i/o x xx - o1 x x port b7 analog input 7 - 28 24 16 - - pb6/ain6 i/o x xx - o1 x x port b6 analog input 6 - 29 25 17 11 11 pb5/ain5 i/o x xx - o1 x x port b5 analog input 5 i 2 c_sda [afr6] 30 26 18 12 12 pb4/ain4 i/o x xx - o1 x x port b4 analog input 4 i 2 c_scl [afr6] 31 27 19 13 13 pb3/ain3 i/o x xx - o1 x x port b3 analog input 3 tim1_etr [afr5] 32 28 20 14 14 pb2/ain2 i/o x xx - o1 x x port b2 analog input tim1_ch3n [afr5] 33 29 21 15 15 pb1/ain1 i/o x xx - o1 x x port b1 analog input 1 tim1_ch2n [afr5] 34 30 22 16 16 pb0/ain0 i/o x xx - o1 x x port b0 analog input 0 tim1_ch1n [afr5] 35 - - - - ph4/tim1_etr i/o x x- - o1 x x port h4 timer 1 - trigger input - 36---- ph5/ tim1_ch3n i/o x x- - o1 x x port h5 timer 1 - inverted channel 3 - 37---- ph6/ tim1_ch2n i/o x x- - o1 x x port h6 timer 1 - inverted channel 2 - table 11. stm8af526x/8x/ax and stm8af 6269/8x/ax pin description (continued) pin number pin name type input output main function (after reset) default alternate function alternate function after remap [option bit] lqfp80 lqfp64 lqfp48 stm8af62xx lqfp32/vfqfpn32 stm8af52x6 vfqfpn32 floating wpu ext. interrupt high sink speed od pp pinouts and pin description stm8af526x/8x/ax stm8af6269/8x/ax 36/125 docid14395 rev 15 38---- ph7/ tim1_ch1n i/o x x- - o1 x x port h7 timer 1 - inverted channel 2 - 39 31 23 - - pe7/ain8 i/o x x- - o1 x x port e7 analog input 8 - 40 32 24 pe6/ain9 i/o x xx - o1 x x port e6 analog input 9 - 41 33 25 17 17 pe5/spi_nss (2) i/o x xx - o1 x x port e5 spi master/ slave select - 42 - - - - pc0/adc_etr i/o x xx - o1 x x port c0 adc trigger input - 43 34 26 18 18 pc1/tim1_ch1 i/o x xxhso3 x x port c1 timer 1 - channel 1 - 44 35 27 19 19 pc2/tim1_ch2 i/o x xxhso3 x x port c2 timer 1- channel 2 - 45 36 28 20 20 pc3/tim1_ch3 i/o x xxhso3 x x port c3 timer 1 - channel 3 - 46 37 29 21 21 pc4/tim1_ch4 i/o x xxhso3 x x port c4 timer 1 - channel 4 - 47 38 30 22 22 pc5/spi_sck (2) i/o x xx - o3 x x port c5 spi clock - 48 39 31 - - v ssio_2 s - - - - - - - i/o ground - 49 40 32 - - v ddio_2 s - - - - - - - i/o power supply - 50 41 33 23 - pc6/spi_mosi (2) i/o x xx - o3 x x port c6 spi master out/ slave in - 51 42 34 24 - pc7/spi_miso (2) i/o x xx - o3 x x port c7 spi master in/ slave out - 52 43 35 - 23 pg0/can_tx i/o x x- - o1 x x port g0 can transmit - 53 44 36 - 24 pg1/can_rx i/o x x- - o1 x x port g1 can receive - 54 45 - - - pg2 i/o x x- - o1 x x port g2 -- table 11. stm8af526x/8x/ax and stm8af 6269/8x/ax pin description (continued) pin number pin name type input output main function (after reset) default alternate function alternate function after remap [option bit] lqfp80 lqfp64 lqfp48 stm8af62xx lqfp32/vfqfpn32 stm8af52x6 vfqfpn32 floating wpu ext. interrupt high sink speed od pp docid14395 rev 15 37/125 stm8af526x/8x/ax stm8af6269/8x/a x pinouts and pin description 114 55 46 - - - pg3 i/o x x- - o1 x x port g3 -- 56 47 - - - pg4 i/o x x- - o1 x x port g4 -- 57 48 - - - pi0 i/o x x- - o1 x x port i0 -- 58---- pi1 i/o x x- - o1 x x port i1 -- 59---- pi2 i/o x x- - o1 x x port i2 -- 60---- pi3 i/o x x- - o1 x x port i3 -- 61---- pi4 i/o x x- - o1 x x port i4 -- 62---- pi5 i/o x x- - o1 x x port i5 -- 63 49 - - - pg5 i/o x x- - o1 x x port g5 -- 64 50 - - - pg6 i/o x x- - o1 x x port g6 -- 65 51 - - - pg7 i/o x x- - o1 x x port g7 -- 66 52 - - - pe4 i/o x xx - o1 x x port e4 -- 67 53 37 - - pe3/tim1_bkin i/o x xx - o1 x x port e3 timer 1 - break input - 68 54 38 - - pe2/i 2 c_sda i/o x -x - o1t (3) - port e2 i 2 c data - 69 55 39 - - pe1/i 2 c_scl i/o x -x - o1t (3) - port e1 i 2 c clock - 70 56 40 - - pe0/clk_cco i/o x xx - o3 x x port e0 configurab le clock output - 71---- pi6 i/o x x- - o1 x x port i6 -- 72---- pi7 i/o x x- - o1 x x port i7 -- 73 57 41 25 25 pd0/tim3_ch2 i/o x xxhso3 x x port d0 timer 3 - channel 2 tim1_bkin [afr3]/ clk_cco [afr2] 74 58 42 26 26 pd1/swim (4) i/o x x xhs o4 x x port d1 swim data interface - 75 59 43 27 27 pd2/tim3_ch1 i/o x xxhso3 x x port d2 timer 3 - channel 1 tim2_ch3 [afr1] 76 60 44 28 28 pd3/tim2_ch2 i/o x xxhso3 x x port d3 timer 2 - channel 2 adc_etr [afr0] 77 61 45 29 29 pd4/tim2_ch1/ beep i/o x xxhso3 x x port d4 timer 2 - channel 1 beep output [afr7] table 11. stm8af526x/8x/ax and stm8af 6269/8x/ax pin description (continued) pin number pin name type input output main function (after reset) default alternate function alternate function after remap [option bit] lqfp80 lqfp64 lqfp48 stm8af62xx lqfp32/vfqfpn32 stm8af52x6 vfqfpn32 floating wpu ext. interrupt high sink speed od pp pinouts and pin description stm8af526x/8x/ax stm8af6269/8x/ax 38/125 docid14395 rev 15 78 62 46 30 30 pd5/ linuart_tx i/o x xx - o1 x x port d5 linuart data transmit - 79 63 47 31 31 pd6/ linuart_rx i/o x xx - o1 x x port d6 linuart data receive - 80 64 48 32 32 pd7/tli (5) i/o x xx - o1 x x port d7 top level interrupt - 1. in halt/active-halt mode, this pin behaves as follows: - the input/output path is disabled. - if the hse clock is used for wakeup, the internal weak pull-up is disabled. - if the hse clock is off, the internal weak pull-up setting is used. it is configured through px_cr1[7:0] bits of the corresponding port control register. px_cr1[7:0] bits must be se t correctly to ensure that the pin is not left floating in halt/active-halt mode. 2. spi and ustart are not available in stm8af5286uc, refer to figure 7: stm8af52x6 vfqfpn32 32-pin pinout for the pin names. 3. in the open-drain output column, ?t? defines a true open-drai n i/o (p-buffer, week pull-up and protection diode to v dd are not implemented) 4. the pd1 pin is in input pull-up during the reset phase and after reset release. 5. if this pin is configured as interru pt pin, it will trigger the tli. table 11. stm8af526x/8x/ax and stm8af 6269/8x/ax pin description (continued) pin number pin name type input output main function (after reset) default alternate function alternate function after remap [option bit] lqfp80 lqfp64 lqfp48 stm8af62xx lqfp32/vfqfpn32 stm8af52x6 vfqfpn32 floating wpu ext. interrupt high sink speed od pp docid14395 rev 15 39/125 stm8af526x/8x/ax stm8af6269/8x/a x pinouts and pin description 114 6.2 alternate func tion remapping as shown in the rightmost column of table 11 , some alternate functions can be remapped at different i/o ports by programming one of eight afr (alternate function remap) option bits. refer to section 9: option bytes on page 54 . when the remapping option is active, the default alternate function is no longer available. to use an alternate function, the corresponding peripheral must be enabled in the peripheral registers. alternate function remapping does not effect gpio capabilities of the i/o ports (see the gpio section of stm8s series and stm8af se ries 8-bit microcontrollers reference manual, rm0016). memory and register map stm8af526x/8x/ax stm8af6269/8x/ax 40/125 docid14395 rev 15 7 memory and register map 7.1 memory map figure 8. register and memory map 8 s w r . e \ w h r i ) o d v k s u r j u d p p h p r u \ [ . e \ w h 5 $ 0 v w d f n [ x s w r . e \ w h g d w d ( ( 3 5 2 0 5 h v h u y h g ) o d v k s u r j u d p p h p r u \ h q g d g g u h v v , q w h u u x s w y h f w r u v [ [ [ & 3 8 6 : , 0 g h e x j , 7 & u h j l v w h u v [ ) 5 h v h u y h g 5 h v h u y h g 2 s w l r q e \ w h v [ [ [ 5 h v h u y h g + d u g z d u h u h j l v w h u v [ [ . e \ w h r i % r r w 5 2 0 0 6 9 [ [ ) ) docid14395 rev 15 41/125 stm8af526x/8x/ax stm8af6269/8x/ax memory and register map 114 7.2 register map in this section the memory and register map of the devices covered by this datasheet is described. for a detailed description of the functionality of the registers, refer to stm8s series and stm8af series 8-bit microcontrollers reference manual, rm0016. table 12. memory model 128k flash program memory size flash program memory end address ram size ram end address stack roll-over address 128 k 0x00 27fff 6 k 0x00 17ff 0x00 1400 64 k 0x00 17fff 32 k 0x00 0ffff table 13. i/o port hardware register map address block register label register name reset status 0x00 5000 port a pa_odr port a data outp ut latch register 0x00 0x00 5001 pa_idr port a input pin value register 0xxx (1) 0x00 5002 pa_ddr port a data direction register 0x00 0x00 5003 pa_cr1 port a control register 1 0x00 0x00 5004 pa_cr2 port a control register 2 0x00 0x00 5005 port b pb_odr port b data output latch register 0x00 0x00 5006 pb_idr port b input pin value register 0xxx (1) 0x00 5007 pb_ddr port b data direction register 0x00 0x00 5008 pb_cr1 port b control register 1 0x00 0x00 5009 pb_cr2 port b control register 2 0x00 0x00 500a port c pc_odr port c data output latch register 0x00 0x00 500b pb_idr port c input pin value register 0xxx (1) 0x00 500c pc_ddr port c data direction register 0x00 0x00 500d pc_cr1 port c control register 1 0x00 0x00 500e pc_cr2 port c control register 2 0x00 0x00 500f port d pd_odr port d data output latch register 0x00 0x00 5010 pd_idr port d input pin value register 0xxx (1) 0x00 5011 pd_ddr port d data direction register 0x00 0x00 5012 pd_cr1 port d control register 1 0x02 0x00 5013 pd_cr2 port d control register 2 0x00 memory and register map stm8af526x/8x/ax stm8af6269/8x/ax 42/125 docid14395 rev 15 0x00 5014 port e pe_odr port e data output latch register 0x00 0x00 5015 pe_idr port e input pin value register 0xxx (1) 0x00 5016 pe_ddr port e data direction register 0x00 0x00 5017 pe_cr1 port e control register 1 0x00 0x00 5018 pe_cr2 port e control register 2 0x00 0x00 5019 port f pf_odr port f data output latch register 0x00 0x00 501a pf_idr port f input pin value register 0xxx (1) 0x00 501b pf_ddr port f data direction register 0x00 0x00 501c pf_cr1 port f control register 1 0x00 0x00 501d pf_cr2 port f control register 2 0x00 0x00 501e port g pg_odr port g data out put latch register 0x00 0x00 501f pg_idr port g input pin value register 0xxx (1) 0x00 5020 pg_ddr port g data direction register 0x00 0x00 5021 pg_cr1 port g control register 1 0x00 0x00 5022 pg_cr2 port g control register 2 0x00 0x00 5023 port h ph_odr port h data output latch register 0x00 0x00 5024 ph_idr port h input pin value register 0xxx (1) 0x00 5025 ph_ddr port h data direction register 0x00 0x00 5026 ph_cr1 port h control register 1 0x00 0x00 5027 ph_cr2 port h control register 2 0x00 0x00 5028 port i pi_odr port i data output latch register 0x00 0x00 5029 pi_idr port i input pin value register 0xxx (1) 0x00 502a pi_ddr port i data direction register 0x00 0x00 502b pi_cr1 port i control register 1 0x00 0x00 502c pi_cr2 port i control register 2 0x00 1. depends on the external circuitry. table 13. i/o port hardware register map (continued) address block register label register name reset status docid14395 rev 15 43/125 stm8af526x/8x/ax stm8af6269/8x/ax memory and register map 114 table 14. general hardware register map address block register label register name reset status 0x00 505a flash flash_cr1 flash control register 1 0x00 0x00 505b flash_cr2 flash control register 2 0x00 0x00 505c flash_ncr2 flash complementary control register 2 0xff 0x00 505d flash_fpr flash protection register 0x00 0x00 505e flash_nfpr flash complementary protection register 0xff 0x00 505f flash_iapsr flash in-application programming status register 0x40 0x00 5060 to 0x005061 reserved area (2 bytes) 0x00 5062 flash flash_pukr flash program memory unprotection register 0x00 0x00 5063 reserved area (1 byte) 0x00 5064 flash flash_dukr data eepr om unprotection register 0x00 0x00 5065 to 0x00 509f reserved area (59 bytes) 0x00 50a0 itc exti_cr1 external interrupt control register 1 0x00 0x00 50a1 exti_cr2 external interrupt control register 2 0x00 0x00 50a2 to 0x00 50b2 reserved area (17 bytes) 0x00 50b3 rst rst_sr reset status register 0xxx (1) 0x00 50b4 to 0x00 50bf reserved area (12 bytes) 0x00 50c0 clk clk_ickr internal clock control register 0x01 0x00 50c1 clk_eckr external clock control register 0x00 0x00 50c2 reserved area (1 byte) memory and register map stm8af526x/8x/ax stm8af6269/8x/ax 44/125 docid14395 rev 15 0x00 50c3 clk clk_cmsr clock master status register 0xe1 0x00 50c4 clk_swr clock mast er switch register 0xe1 0x00 50c5 clk_swcr clock switch control register 0xxx 0x00 50c6 clk_ckdivr clock divider register 0x18 0x00 50c7 clk_pckenr1 peripheral clock gating register 1 0xff 0x00 50c8 clk_cssr clock security system register 0x00 0x00 50c9 clk_ccor configurable clock control register 0x00 0x00 50ca clk_pckenr2 peripheral clock gating register 2 0xff 0x00 50cb reserved area (1 byte) 0x00 50cc clk_hsitrimr hsi clock calibration trimming register 0x00 0x00 50cd clk_swimccr swim clock control register 0bxxxx xxx0 0x00 50ce to 0x00 50d0 reserved area (3 bytes) 0x00 50d1 wwdg wwdg_cr wwdg control register 0x7f 0x00 50d2 wwdg_wr wwdr window register 0x7f 0x00 50d3 to 0x00 50df reserved area (13 bytes) 0x00 50e0 iwdg iwdg_kr iwdg key register 0xxx (2) 0x00 50e1 iwdg_pr iwdg prescaler register 0x00 0x00 50e2 iwdg_rlr iwdg reload register 0xff 0x00 50e3 to 0x00 50ef reserved area (13 bytes) 0x00 50f0 awu awu_csr1 awu control/status register 1 0x00 0x00 50f1 awu_apr awu asynchronous prescaler buffer register 0x3f 0x00 50f2 awu_tbr awu timebase selection register 0x00 0x00 50f3 beep beep_csr beep contro l/status register 0x1f 0x00 50f4 to 0x00 50ff reserved area (12 bytes) table 14. general hardware register map (continued) address block register label register name reset status docid14395 rev 15 45/125 stm8af526x/8x/ax stm8af6269/8x/ax memory and register map 114 0x00 5200 spi spi_cr1 spi control register 1 0x00 0x00 5201 spi_cr2 spi control register 2 0x00 0x00 5202 spi_icr spi interrupt control register 0x00 0x00 5203 spi_sr spi st atus register 0x02 0x00 5204 spi_dr spi data register 0x00 0x00 5205 spi_crcpr spi crc polynomial register 0x07 0x00 5206 spi_rxcrcr spi rx crc register 0xff 0x00 5207 spi_txcrcr spi tx crc register 0xff 0x00 5208 to 0x00 520f reserved area (8 bytes) 0x00 5210 i2c i2c_cr1 i2c control register 1 0x00 0x00 5211 i2c_cr2 i2c control register 2 0x00 0x00 5212 i2c_freqr i2c frequency register 0x00 0x00 5213 i2c_oarl i2c own address register low 0x00 0x00 5214 i2c_oarh i2c own address register high 0x00 0x00 5215 0x00 5216 i2c_dr i2c data register 0x00 0x00 5217 i2c_sr1 i2c status register 1 0x00 0x00 5218 i2c_sr2 i2c status register 2 0x00 0x00 5219 i2c_sr3 i2c status register 3 0x00 0x00 521a i2c_itr i2c interrupt control register 0x00 0x00 521b i2c_ccrl i2c clock control register low 0x00 0x00 521c i2c_ccrh i2c clock control register high 0x00 0x00 521d i2c_triser i2c trise register 0x02 0x00 521e to 0x00 522f reserved area (18 bytes) table 14. general hardware register map (continued) address block register label register name reset status memory and register map stm8af526x/8x/ax stm8af6269/8x/ax 46/125 docid14395 rev 15 0x00 5230 usart uart1_sr usart status register 0xc0 0x00 5231 uart1_dr usart data register 0xxx 0x00 5232 uart1_brr1 usart baud rate register 1 0x00 0x00 5233 uart1_brr2 usart baud rate register 2 0x00 0x00 5234 uart1_cr1 usart control register 1 0x00 0x00 5235 uart1_cr2 usart control register 2 0x00 0x00 5236 uart1_cr3 usart control register 3 0x00 0x00 5237 uart1_cr4 usart control register 4 0x00 0x00 5238 uart1_cr5 usart control register 5 0x00 0x00 5239 uart1_gtr usart guard time register 0x00 0x00 523a uart1_pscr usart prescaler register 0x00 0x00 523b to 0x00 523f reserved area (5 bytes) 0x00 5240 linuart uart3_sr linuart status register 0xc0 0x00 5241 uart3_dr linuart data register 0xxx 0x00 5242 uart3_brr1 linuart baud rate register 1 0x00 0x00 5243 uart3_brr2 linuart baud rate register 2 0x00 0x00 5244 uart3_cr1 linuart control register 1 0x00 0x00 5245 uart3_cr2 linuart control register 2 0x00 0x00 5246 uart3_cr3 linuart control register 3 0x00 0x00 5247 uart3_cr4 linuart control register 4 0x00 0x00 5248 reserved 0x00 5249 uart3_cr6 linuart control register 6 0x00 0x00 524a to 0x00 524f reserved area (6 bytes) table 14. general hardware register map (continued) address block register label register name reset status docid14395 rev 15 47/125 stm8af526x/8x/ax stm8af6269/8x/ax memory and register map 114 0x00 5250 tim1 tim1_cr1 tim1 control register 1 0x00 0x00 5251 tim1_cr2 tim1 control register 2 0x00 0x00 5252 tim1_smcr tim1 slave mode control register 0x00 0x00 5253 tim1_etr tim1 exte rnal trigger register 0x00 0x00 5254 tim1_ier tim1 inte rrupt enable register 0x00 0x00 5255 tim1_sr1 tim1 status register 1 0x00 0x00 5256 tim1_sr2 tim1 status register 2 0x00 0x00 5257 tim1_egr tim1 event generation register 0x00 0x00 5258 tim1_ccmr1 tim1 captur e/compare mode register 1 0x00 0x00 5259 tim1_ccmr2 tim1 captur e/compare mode register 2 0x00 0x00 525a tim1_ccmr3 tim1 captur e/compare mode register 3 0x00 0x00 525b tim1_ccmr4 tim1 captur e/compare mode register 4 0x00 0x00 525c tim1_ccer1 tim1 captur e/compare enable register 1 0x00 0x00 525d tim1_ccer2 tim1 captur e/compare enable register 2 0x00 0x00 525e tim1_cntrh tim1 counter high 0x00 0x00 525f tim1_cntrl tim1 counter low 0x00 0x00 5260 tim1_pscrh tim1 prescaler register high 0x00 0x00 5261 tim1_pscrl tim1 prescaler register low 0x00 0x00 5262 tim1_arrh tim1 auto-reload register high 0xff 0x00 5263 tim1_arrl tim1 auto-reload register low 0xff 0x00 5264 tim1_rcr tim1 repetit ion counter register 0x00 0x00 5265 tim1_ccr1h tim1 capture/ compare register 1 high 0x00 0x00 5266 tim1_ccr1l tim1 captur e/compare register 1 low 0x00 0x00 5267 tim1_ccr2h tim1 capture/ compare register 2 high 0x00 0x00 5268 tim1_ccr2l tim1 captur e/compare register 2 low 0x00 0x00 5269 tim1_ccr3h tim1 capture/ compare register 3 high 0x00 0x00 526a tim1_ccr3l tim1 captur e/compare register 3 low 0x00 0x00 526b tim1_ccr4h tim1 capture/ compare register 4 high 0x00 0x00 526c tim1_ccr4l tim1 captur e/compare register 4 low 0x00 0x00 526d tim1_bkr tim1 break register 0x00 0x00 526e tim1_dtr tim1 dead-time register 0x00 0x00 526f tim1_oisr tim1 output idle state register 0x00 0x00 5270 to 0x00 52ff reserved area (147 bytes) table 14. general hardware register map (continued) address block register label register name reset status memory and register map stm8af526x/8x/ax stm8af6269/8x/ax 48/125 docid14395 rev 15 0x00 5300 tim2 tim2_cr1 tim2 control register 1 0x00 0x00 5301 tim2_ier tim2 interrupt enable register 0x00 0x00 5302 tim2_sr1 tim2 status register 1 0x00 0x00 5303 tim2_sr2 tim2 status register 2 0x00 0x00 5304 tim2_egr tim2 event generation register 0x00 0x00 5305 tim2_ccmr1 tim2 captur e/compare mode register 1 0x00 0x00 5306 tim2_ccmr2 tim2 captur e/compare mode register 2 0x00 0x00 5307 tim2_ccmr3 tim2 captur e/compare mode register 3 0x00 0x00 5308 tim2_ccer1 tim2 captur e/compare enable register 1 0x00 0x00 5309 tim2_ccer2 tim2 captur e/compare enable register 2 0x00 0x00 530a tim2_cntrh tim2 counter high 0x00 0x00 530b tim2_cntrl tim2 counter low 0x00 00 530c0x tim2_pscr tim2 prescaler register 0x00 0x00 530d tim2_arrh tim2 auto-reload register high 0xff 0x00 530e tim2_arrl tim2 auto-reload register low 0xff 0x00 530f tim2_ccr1h tim2 capture/ compare register 1 high 0x00 0x00 5310 tim2_ccr1l tim2 captur e/compare register 1 low 0x00 0x00 5311 tim2_ccr2h tim2 capture/compare reg. 2 high 0x00 0x00 5312 tim2_ccr2l tim2 captur e/compare register 2 low 0x00 0x00 5313 tim2_ccr3h tim2 capture/ compare register 3 high 0x00 0x00 5314 tim2_ccr3l tim2 captur e/compare register 3 low 0x00 0x00 5315 to 0x00 531f reserved area (11 bytes) table 14. general hardware register map (continued) address block register label register name reset status docid14395 rev 15 49/125 stm8af526x/8x/ax stm8af6269/8x/ax memory and register map 114 0x00 5320 tim3 tim3_cr1 tim3 control register 1 0x00 0x00 5321 tim3_ier tim3 interrupt enable register 0x00 0x00 5322 tim3_sr1 tim3 status register 1 0x00 0x00 5323 tim3_sr2 tim3 status register 2 0x00 0x00 5324 tim3_egr tim3 event generation register 0x00 0x00 5325 tim3_ccmr1 tim3 captur e/compare mode register 1 0x00 0x00 5326 tim3_ccmr2 tim3 captur e/compare mode register 2 0x00 0x00 5327 tim3_ccer1 tim3 captur e/compare enable register 1 0x00 0x00 5328 tim3_cntrh tim3 counter high 0x00 0x00 5329 tim3_cntrl tim3 counter low 0x00 0x00 532a tim3_pscr tim3 prescaler register 0x00 0x00 532b tim3_arrh tim3 auto-reload register high 0xff 0x00 532c tim3_arrl tim3 auto-reload register low 0xff 0x00 532d tim3_ccr1h tim3 captur e/compare register 1 high 0x00 0x00 532e tim3_ccr1l tim3 captur e/compare register 1 low 0x00 0x00 532f tim3_ccr2h tim3 capture/ compare register 2 high 0x00 0x00 5330 tim3_ccr2l tim3 captur e/compare register 2 low 0x00 0x00 5331 to 0x00 533f reserved area (15 bytes) 0x00 5340 tim4 tim4_cr1 tim4 control register 1 0x00 0x00 5341 tim4_ier tim4 interrupt enable register 0x00 0x00 5342 tim4_sr tim4 status register 0x00 0x00 5343 tim4_egr tim4 event generation register 0x00 0x00 5344 tim4_cntr tim4 counter 0x00 0x00 5345 tim4_pscr tim4 prescaler register 0x00 0x00 5346 tim4_arr tim4 auto-reload register 0xff 0x00 5347 to 0x00 53ff reserved area (185 bytes) table 14. general hardware register map (continued) address block register label register name reset status memory and register map stm8af526x/8x/ax stm8af6269/8x/ax 50/125 docid14395 rev 15 0x00 5400 adc adc _csr adc control/status register 0x00 0x00 5401 adc_cr1 adc confi guration register 1 0x00 0x00 5402 adc_cr2 adc confi guration register 2 0x00 0x00 5403 adc_cr3 adc confi guration register 3 0x00 0x00 5404 adc_drh adc data register high 0xxx 0x00 5405 adc_drl adc data register low 0xxx 0x00 5406 adc_tdrh adc schmitt trig ger disable register high 0x00 0x00 5407 adc_tdrl adc schmitt trigger disable register low 0x00 0x00 5408 to 0x00 541f reserved area (24 bytes) 0x00 5420 becan can_mcr can master c ontrol register 0x02 0x00 5421 can_msr can master status register 0x02 0x00 5422 can_tsr can transmit status register 0x00 0x00 5423 can_tpr can transmit priority register 0x0c 0x00 5424 can_rfr can receive fifo register 0x00 0x00 5425 can_ier can interr upt enable register 0x00 0x00 5426 can_dgr can diagnosis register 0x0c 0x00 5427 can_fpsr can page selection register 0x00 0x00 5428 can_p0 can paged register 0 0xxx (3) 0x00 5429 can_p1 can paged register 1 0xxx (3) 0x00 542a can_p2 can paged register 2 0xxx (3) 0x00 542b can_p3 can paged register 3 0xxx (3) 0x00 542c can_p4 can paged register 4 0xxx (3) 0x00 542d can_p5 can paged register 5 0xxx (3) 0x00 542e can_p6 can paged register 6 0xxx (3) 0x00 542f can_p7 can paged register 7 0xxx (3) 0x00 5430 can_p8 can paged register 8 0xxx (3) 0x00 5431 can_p9 can paged register 9 0xxx (3) 0x00 5432 can_pa can paged register a 0xxx (3) 0x00 5433 can_pb can paged register b 0xxx (3) 0x00 5434 can_pc can paged register c 0xxx (3) 0x00 5435 can_pd can paged register d 0xxx (3) 0x00 5436 can_pe can paged register e 0xxx (3) table 14. general hardware register map (continued) address block register label register name reset status docid14395 rev 15 51/125 stm8af526x/8x/ax stm8af6269/8x/ax memory and register map 114 0x00 5437 becan can_pf can paged register f 0xxx (3) 0x00 5438 to 0x00 57ff reserved area (968 bytes) 1. depends on the previous reset source. 2. write only register. 3. if the bootloader is enabled, it is initialized to 0x00. table 14. general hardware register map (continued) address block register label register name reset status table 15. cpu/swim/debug module/interrupt controller registers address block register label register name reset status 0x00 7f00 cpu (1) a accumulator 0x00 0x00 7f01 pce program counter extended 0x00 0x00 7f02 pch program counter high 0x80 0x00 7f03 pcl program counter low 0x00 0x00 7f04 xh x index register high 0x00 0x00 7f05 xl x index register low 0x00 0x00 7f06 yh y index register high 0x00 0x00 7f07 yl y index register low 0x00 0x00 7f08 sph stack pointer high 0x17 (2) 0x00 7f09 spl stack pointer low 0xff 0x00 7f0a cc condition code register 0x28 0x00 7f0b to 0x00 7f5f reserved area (85 bytes) 0x00 7f60 cpu cfg_gcr global co nfiguration register 0x00 0x00 7f70 itc itc_spr1 interrupt so ftware priority register 1 0xff 0x00 7f71 itc_spr2 interrupt software priority register 2 0xff 0x00 7f72 itc_spr3 interrupt software priority register 3 0xff 0x00 7f73 itc_spr4 interrupt software priority register 4 0xff 0x00 7f74 itc_spr5 interrupt software priority register 5 0xff 0x00 7f75 itc_spr6 interrupt software priority register 6 0xff 0x00 7f76 itc_spr7 interrupt software priority register 7 0xff 0x00 7f77 itc_spr8 interrupt software priority register 8 0xff 0x00 7f78 to 0x00 7f79 reserved area (2 bytes) 0x00 7f80 swim swim_csr swim control status register 0x00 memory and register map stm8af526x/8x/ax stm8af6269/8x/ax 52/125 docid14395 rev 15 0x00 7f81 to 0x00 7f8f reserved area (15 bytes) 0x00 7f90 dm dm_bk1re dm breakpoint 1 r egister extended byte 0xff 0x00 7f91 dm_bk1rh dm breakpoint 1 register high byte 0xff 0x00 7f92 dm_bk1rl dm breakpoint 1 register low byte 0xff 0x00 7f93 dm_bk2re dm breakpoint 2 register extended byte 0xff 0x00 7f94 dm_bk2rh dm breakpoint 2 register high byte 0xff 0x00 7f95 dm_bk2rl dm breakpoint 2 register low byte 0xff 0x00 7f96 dm_cr1 dm debug modul e control register 1 0x00 0x00 7f97 dm_cr2 dm debug modul e control register 2 0x00 0x00 7f98 dm_csr1 dm debug module control/status register 1 0x10 0x00 7f99 dm_csr2 dm debug module control/status register 2 0x00 0x00 7f9a dm_enfctr dm enable function register 0xff 0x00 7f9b to 0x00 7f9f reserved area (5 bytes) 1. accessible by debug module only 2. product dependent value, see figure 8: register and memory map . table 15. cpu/swim/debug module/interrupt controller registers (continued) address block register label register name reset status table 16. temporary memory unprotection registers address block register label register name reset status 0x00 5800 tmu tmu_k1 temporary memory unprotection key register 1 0x00 0x00 5801 tmu_k2 temporary memory unprotection key register 2 0x00 0x00 5802 tmu_k3 temporary memory unprotection key register 3 0x00 0x00 5803 tmu_k4 temporary memory unprotection key register 4 0x00 0x00 5804 tmu_k5 temporary memory unprotection key register 5 0x00 0x00 5805 tmu_k6 temporary memory unprotection key register 6 0x00 0x00 5806 tmu_k7 temporary memory unprotection key register 7 0x00 0x00 5807 tmu_k8 temporary memory unprotection key register 8 0x00 0x00 5808 tmu_csr temporary memory unprotec tion control and status register 0x00 docid14395 rev 15 53/125 stm8af526x/8x/ax stm8af6269/8x/ax interrupt table 114 8 interrupt table table 17. stm8a interrupt table (1) priority source block description interrupt vector address wakeup from halt comments - reset reset 0x00 8000 yes - - trap sw interrupt 0x00 8004 - - 0 tli external top level interrupt 0x00 8008 - - 1 awu auto-wakeup from halt 0x00 800c yes - 2 clock controller main clock controller 0x00 8010 - - 3 misc external interrupt e0 0x00 8014 yes port a interrupts 4 misc external interrupt e1 0x00 8018 yes port b interrupts 5 misc external interrupt e2 0x00 801c yes port c interrupts 6 misc external interrupt e3 0x00 8020 yes port d interrupts 7 misc external interrupt e4 0x00 8024 yes port e interrupts 8 can can interrupt rx 0x00 8028 yes - 9 can can interrupt tx/er/sc 0x00 802c - - 10 spi end of transfer 0x00 8030 yes - 11 timer 1 update/overflow/ trigger/break 0x00 8034 - - 12 timer 1 capture/compare 0x00 8038 - - 13 timer 2 update/overflow 0x00 803c - - 14 timer 2 capture/compare 0x00 8040 - - 15 timer 3 update/overflow 0x00 8044 - - 16 timer 3 capture/compare 0x00 8048 - - 17 usart tx complete 0x00 804c - - 18 usart receive data full reg. 0x00 8050 - - 19 i 2 c i 2 c interrupts 0x00 8054 yes - 20 linuart tx complete/error 0x00 8058 - - 21 linuart receive data full reg. 0x00 805c - - 22 adc end of conversion 0x00 8060 - - 23 timer 4 update/overflow 0x00 8064 - - 24 eeprom end of programming/ write in not allowed area 0x00 8068 - - 1. all unused interrupts must be initialized with ?iret? for robust programming. option bytes stm8af526x/8x/ax stm8af6269/8x/ax 54/125 docid14395 rev 15 9 option bytes option bytes contain configurations for device hardware features as well as the memory protection of the device. they are stored in a dedicated block of the memory. each option byte has to be stored twice, for redundancy, in a regular form (optx) and a complemented one (noptx), except for the rop (read-out prot ection) option byte and option bytes 8 to 16. option bytes can be modified in icp mode (via swim) by access ing the eeprom address shown in table 18: option bytes below. option bytes can also be modified ?on the fly? by the application in iap mode, except the rop and ubc options that can only be changed in icp mode (via swim). refer to the stm8 flash programming manual (pm0047) and stm8 swim communication protocol and debug module user manual (um0470) for information on swim programming procedures. table 18. option bytes addr. option name option byte no. option bits factory default setting 76543 2 1 0 0x00 4800 read-out protection (rop) opt0 rop[7:0] 0x00 0x00 4801 user boot code (ubc) opt1 ubc[7:0] 0x00 0x00 4802 nopt1 nubc[7:0] 0xff 0x00 4803 alternate function remapping (afr) opt2 afr7 afr6 afr5 afr4 afr3 afr2 afr1 afr0 0x00 0x00 4804 nopt2 nafr7 nafr6 nafr5 nafr4 nafr3 nafr2 nafr1 nafr0 0xff 0x00 4805 watchdog option opt3 reserved lsi_ en iwdg _hw wwd g _hw wwdg _halt 0x00 0x00 4806 nopt3 reserved nlsi_ en niwd g_hw nwwd g_hw nwwg _halt 0xff 0x00 4807 clock option opt4 reserved ext clk ckaw usel prsc1 prsc0 0x00 0x00 4808 nopt4 reserved next clk nckaw usel nprsc1 nprsc 0 0xff 0x00 4809 hse clock startup opt5 hsecnt[7:0] 0x00 0x00 480a nopt5 nhsecnt[7:0] 0xff docid14395 rev 15 55/125 stm8af526x/8x/ax stm8af6269/8x/ax option bytes 114 0x00 480b tmu opt6 tmu[3:0] 0x00 0x00 480c nopt6 ntmu[3:0] 0xff 0x00 480d flash wait states opt7 reserved wait state 0x00 0x00 480e nopt7 reserved nwait state 0xff 0x00 480f reserved 0x00 4810 tmu opt8 tmu_key 1 [7:0] 0x00 0x00 4811 opt9 tmu_key 2 [7:0] 0x00 0x00 4812 opt10 tmu_key 3 [7:0] 0x00 0x00 4813 opt11 tmu_key 4 [7:0] 0x00 0x00 4814 opt12 tmu_key 5 [7:0] 0x00 0x00 4815 opt13 tmu_key 6 [7:0] 0x00 0x00 4816 opt14 tmu_key 7 [7:0] 0x00 0x00 4817 opt15 tmu_key 8 [7:0] 0x00 0x00 4818 opt16 tmu_maxatt [7:0] 0xc7 0x00 4819 to 487d reserved 0x00 487e boot- loader (1) opt17 bl [7:0] 0x00 0x00 487f nopt 17 nbl [7:0] 0xff 1. this option consists of two bytes that must have a complementar y value in order to be valid. if the option is invalid, it has no effect on emc reset. table 18. option bytes (continued) addr. option name option byte no. option bits factory default setting 76543 2 1 0 option bytes stm8af526x/8x/ax stm8af6269/8x/ax 56/125 docid14395 rev 15 table 19. option byte description option byte no. description opt0 rop[7:0]: memory readout protection (rop) 0xaa: enable readout protection (w rite access via swim protocol) note: refer to stm8s series and stm8 af series 8-bit microcontrollers reference manual (rm0016) se ction on flash/eeprom memory readout protection for details. opt1 ubc[7:0]: user boot code area 0x00: no ubc, no write-protection 0x01: page 0 to 1 defined as ubc, memory write-protected 0x02: page 0 to 3 defined as ubc, memory write-protected 0x03 to 0xff: pages 4 to 255 defined as ubc, memory write-protected note: refer to stm8s series and stm8 af series 8-bit microcontrollers reference manual (rm0016) sectio n on flash/eeprom write protection for more details. opt2 afr7: alternate function remapping option 7 0: port d4 alternate function = tim2_ch1 1: port d4 alternate function = beep afr6: alternate function remapping option 6 0: port b5 alternate function = ai n5, port b4 alternate function = ain4 1: port b5 alternate function = i 2 c_sda, port b4 al ternate function = i 2 c_scl. afr5: alternate function remapping option 5 0: port b3 alternate f unction = ain3, port b2 alternate function = ain2, port b1 alternate function = ain1, port b0 alternate function = ain0. 1: port b3 alternate function = ti m1_etr, port b2 alternate function = tim1_ch3n, port b1 alternate function = tim1_ch2n, port b0 alternate function = tim1_ch1n. afr4: alternate function remapping option 4 0: port d7 alternate function = tli 1: reserved afr3: alternate function remapping option 3 0: port d0 alternate function = tim3_ch2 1: port d0 alternate function = tim1_bkin afr2: alternate function remapping option 2 0: port d0 alternate function = tim3_ch2 1: port d0 alternate function = clk_cco note: afr2 option has priority over afr3 if both are activated afr1: alternate function remapping option 1 0: port a3 alternate function = ti m2_ch3, port d2 alternate function tim3_ch1. 1: port a3 alternate function = ti m3_ch1, port d2 alternate function tim2_ch3. afr0: alternate function remapping option 0 0: port d3 alternate function = tim2_ch2 1: port d3 alternate function = adc_etr docid14395 rev 15 57/125 stm8af526x/8x/ax stm8af6269/8x/ax option bytes 114 opt3 lsi_en: low speed internal clock enable 0: lsi clock is not available as cpu clock source 1: lsi clock is available as cpu clock source iwdg_hw: independent watchdog 0: iwdg independent watchdog activated by software 1: iwdg independent watchd og activated by hardware wwdg_hw: window watchdog activation 0: wwdg window watchdog activated by software 1: wwdg window watchdog activated by hardware wwdg_halt: window watchdog reset on halt 0: no reset generated on halt if wwdg active 1: reset generated on halt if wwdg active opt4 extclk: external clock selection 0: external crystal connected to oscin/oscout 1: external clock signal on oscin ckawusel: auto-wakeup unit/clock 0: lsi clock source selected for awu 1: hse clock with prescaler sele cted as clock source for awu prsc[1:0]: awu clock prescaler 00: 24 mhz to 128 khz prescaler 01: 16 mhz to 128 khz prescaler 10: 8 mhz to 128 khz prescaler 11: 4 mhz to 128 khz prescaler opt5 hsecnt[7:0]: hse crystal oscillator stabilization time this configures the stabilization time to 0.5, 8, 128, and 2048 hse cycles with corresponding option byte values of 0xe1, 0xd2, 0xb4, and 0x00. opt6 tmu [3:0]: enable temporary memory unprotection 0101: tmu disabled (permanent rop). any other value: tmu enabled. opt7 wait state: wait state configuration this option configures the number of wait states inserted when reading from the flash/data eeprom memory. 0: no wait state 1: one wait state opt8 tmu_key 1 [7:0]: temporary unprotection key 0 temporary unprotection key: must be different from 0x00 or 0xff opt9 tmu_key 2 [7:0]: temporary unprotection key 1 temporary unprotection key: must be different from 0x00 or 0xff opt10 tmu_key 3 [7:0]: temporary unprotection key 2 temporary unprotection key: must be different from 0x00 or 0xff opt11 tmu_key 4 [7:0]: temporary unprotection key 3 temporary unprotection key: must be different from 0x00 or 0xff table 19. option byte description (continued) option byte no. description option bytes stm8af526x/8x/ax stm8af6269/8x/ax 58/125 docid14395 rev 15 opt12 tmu_key 5 [7:0]: temporary unprotection key 4 temporary unprotection key: must be different from 0x00 or 0xff opt13 tmu_key 6 [7:0]: temporary unprotection key 5 temporary unprotection key: must be different from 0x00 or 0xff opt14 tmu_key 7 [7:0]: temporary unprotection key 6 temporary unprotection key: must be different from 0x00 or 0xff opt15 tmu_key 8 [7:0]: temporary unprotection key 7 temporary unprotection key: must be different from 0x00 or 0xff opt16 tmu_maxatt [7:0]: tmu access failure counter tmu_maxatt can be initialized with the desired value only if tmu is disabled (tmu[3:0]=0101 in opt6 option byte). when tmu is enabled, any attemp t to temporary remove the readout protection by using wrong key values increments the counter. when the option byte value reaches 0x08, the flash memory and data eeprom are erased. opt17 bl[7:0]: bootlo ader enable if this option byte is set to 0x55 (complementary value 0xaa) the bootloader program is activated also in case of a programmed code memory (for more details, see th e bootloader user manual, um0560). table 19. option byte description (continued) option byte no. description docid14395 rev 15 59/125 stm8af526x/8x/ax stm8af6269/8x/ax electrical characteristics 114 10 electrical characteristics 10.1 parameter conditions unless otherwise specified, all voltages are referred to v ss . 10.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = -40 c, t a = 25 c, and t a = t amax (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. 10.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 5.0 v. they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range . 10.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 10.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 9 . figure 9. pin loading conditions 6 7 0 $ 3 , 1 s ) 0 6 y 9 electrical characteristics stm8a f526x/8x/ax stm8af6269/8x/ax 60/125 docid14395 rev 15 10.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 10 . figure 10. pin input voltage 10.2 absolute maximum ratings stresses above the absolute maximum ratings listed in table 20: voltage characteristics , table 21: current characteristics and table 22: thermal characteristics may cause permanent damage to the device. these are stre ss ratings only, and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may affect th e device?s reliability. the devic e?s mission profile (application conditions) is compliant with the jedec jesd47 qualification standard, extended mission profiles are available on demand. 6 7 0 $ 3 , 1 0 6 y 9 9 , 1 table 20. voltage characteristics symbol ratings min max unit v ddx - v ss supply voltage (including v dda and v ddio ) (1) 1. all power (v dd , v ddio , v dda ) and ground (v ss , v ssio , v ssa ) pins must always be connected to the external power supply -0.3 6.5 v v in input voltage on true open drain pins (pe1, pe2) (2) 2. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in > v dd while a negative injection is induced by v in < v ss . for true open-drain pads, there is no positive injection current, and the corresponding v in maximum must always be respected v ss - 0.3 6.5 input voltage on any other pin (2) v ss - 0.3 v dd + 0.3 |v ddx - v dd | variations between different power pins - 50 mv |v ssx - v ss | variations between all the different ground pins - 50 v esd electrostatic discharge voltage see absolute maximum ratings (electrical sensitivity) on page 88 docid14395 rev 15 61/125 stm8af526x/8x/ax stm8af6269/8x/ax electrical characteristics 114 table 21. current characteristics symbol ratings max. unit i vddio total current into v ddio power lines (source) (1)(2)(3) 1. all power (v dd , v ddio , v dda ) and ground (v ss , v ssio , v ssa ) pins must always be connected to the external supply. 2. the total limit applies to the sum of operation and injected currents. 3. v ddio includes the sum of the positive injection currents. v ssio includes the sum of the negative injection currents. 100 ma i vssio total current out of v ss io ground lines (sink) (1)(2)(3) 100 i io output current sunk by any i/o and control pin 20 output current source by any i/os and control pin -20 i inj(pin) (4) 4. this condition is implic itly insured if vin maximum is respect ed. if vin maximum cannot be respected, the injection current must be limited externally to the iin j(pin) value. a positive in jection is induced by vin > vdd while a negative injection is induced by vin < vss. for true open-drain pads , there is no positive injection current allowed and the corresponding vin maximum must always be respected. injected current on any pin 10 i inj(tot) sum of injected currents 50 table 22. thermal characteristics symbol ratings value unit t stg storage temperature range -65 to 150 c t j maximum junction temperature 160 table 23. operating lifetime (1) 1. for detailed mission profile analysis, please contact th e nearest st sales office. symbol ratings value unit olf conforming to aec-q100 rev g ? 40 to 125 c grade 1 ? 40 to 150 c grade 0 electrical characteristics stm8a f526x/8x/ax stm8af6269/8x/ax 62/125 docid14395 rev 15 10.3 operating conditions figure 11. f cpumax versus v dd table 24. general operating conditions symbol parameter conditions min max unit f cpu internal cpu clock frequency 1 wait state t a = -40 c to 150 c 16 24 mhz 0 wait state t a = -40 c to 150 c 016 v dd/ v ddio standard operating voltage - 3.0 5.5 v v cap (1) 1. care should be taken when selecting the capacitor, due to its tolerance, as well as the parameter dependency on temperature, dc bias and frequency in addi tion to other factors. the parameter maximum value must be respected for the full application range. c ext : capacitance of external capacitor - 470 3300 nf esr of external capacitor at 1 mhz (2) 2. this frequency of 1 mhz as a condition for v cap parameters is given by design of internal regulator. -0.3 esl of external capacitor - 15 nh t a ambient temperature suffix a - 40 85 c suffix c 125 suffix d 150 t j junction temperature range suffix a - 40 90 suffix c 130 suffix d 155 0 6 y 9 ) x q f w l r q d o l w \ q r w j x d u d q w h h g l q w k l v d u h d i & 3 8 > 0 + ] @ 6 x s s o \ y r o w d j h > 9 @ ) x q f w l r q d o l w \ j x d u d q w h h g # 7 $ w r ? & d w z d l w v w d w h ) x q f w l r q d o l w \ j x d u d q w h h g # 7 $ w r ? & d w z d l w v w d w h docid14395 rev 15 63/125 stm8af526x/8x/ax stm8af6269/8x/ax electrical characteristics 114 10.3.1 vcap external capacitor stabilization for the main regula tor is achieved connecting an external capacitor c ext to the v cap pin. c ext is specified in table 24 . care should be taken to limit the series inductance to less than 15 nh. figure 12. external capacitor c ext 1. legend: esr is the equivalent series resist ance and esl is the equivalent inductance. 10.3.2 supply current characteristics the current consumption is measured as described in figure 9 on page 59 and figure 10 on page 60 . if not explicitly stated, general condit ions of temperature and voltage apply. table 25. operating conditi ons at power-up/power-down symbol parameter conditions min typ max unit t vdd v dd rise time rate - 2 (1) 1. guaranteed by design, not tested in production. - 8 s/v v dd fall time rate - 2 (1) - 8 t temp reset release delay v dd rising - 1 1.7 ms reset generation delay v dd falling - 3 - s v it+ power-on reset threshold (2) (3) 2. if v dd is below 3 v, the code execution is guaranteed above the v it- and v it+ thresholds. ram content is kept. the eeprom programming sequence must not be initiated. 3. there is inrush current into v dd present after device power on to charge c ext capacitor. this inrush energy depends from c ext capacitor value. for example, a c ext of 1 f requires q=1 f x 1.8 v = 1.8 c. - 2.65 2.8 2.95 v v it- brown-out reset threshold - 2.58 2.73 2.88 v hys(bor) brown-out reset hysteresis --70 (1) -mv 0 6 y 9 ( 6 5 5 / h d n ( 6 / & electrical characteristics stm8a f526x/8x/ax stm8af6269/8x/ax 64/125 docid14395 rev 15 table 26. total current consumption in run, wait and slow mode. general conditions for v dd apply, t a = ? 40 c to 150 c symbol parameter conditions typ max unit i dd(run) (1) supply current in run mode all peripherals clocked, code executed from flash program memory, hse external clock (without resonator) f cpu = 24 mhz 1 ws 8.7 16.8 (2) ma f cpu = 16 mhz 7.4 14 f cpu = 8 mhz 4.0 7.4 (2) f cpu = 4 mhz 2.4 4.1 (2) f cpu = 2 mhz 1.5 2.5 i dd(run) (1) supply current in run mode all peripherals clocked, code executed from ram, hse external clock (without resonator) f cpu = 24 mhz 4.4 6.0 (2) f cpu = 16 mhz 3.7 5.0 f cpu = 8 mhz 2.2 3.0 (2) f cpu = 4 mhz 1.4 2.0 (2) f cpu = 2 mhz 1.0 1.5 i dd(wfi) (1) supply current in wait mode cpu stopped, all peripherals off, hse external clock f cpu = 24 mhz 2.4 3.1 (2) f cpu = 16 mhz 1.65 2.5 f cpu = 8 mhz 1.15 1.9 (2) f cpu = 4 mhz 0.90 1.6 (2) f cpu = 2 mhz 0.80 1.5 i dd(slow) (1) supply current in slow mode f cpu scaled down, all peripherals off, code executed from ram external clock 16 mhz f cpu = 125 khz 1.50 1.95 lsi internal rc f cpu = 128 khz 1.50 1.80 (2) 1. the current due to i/o utilization is not taken into account in these values. 2. guaranteed by design, not tested in production. docid14395 rev 15 65/125 stm8af526x/8x/ax stm8af6269/8x/ax electrical characteristics 114 current consumption for on-chip peripherals table 27. total current consumption in halt and active-halt modes. general conditions for v dd applied. t a = ? 40 c to 55 c unless otherwise stated symbol parameter conditions typ max unit main voltage regulator (mvr) (1) flash mode (2) clock source and temperature condition i dd(h) supply current in halt mode off power- down clocks stopped 5 35 (3) a clocks stopped, t a = 25 c 525 i dd(ah) supply current in active-halt mode with regulator on on power- down external clock 16 mhz f master = 125 khz 770 900 (3) lsi clock 128 khz 150 230 (3) supply current in active-halt mode with regulator off off power- down lsi clock 128 khz 25 42 (3) lsi clock 128 khz, t a = 25 c 25 30 t wu(ah) wakeup time from active-halt mode with regulator on on operating mode t a = ? 40 to 150 c 10 30 (3) s wakeup time from active-halt mode with regulator off off 50 80 (3) 1. configured by the regah bit in the clk_ickr register. 2. configured by the ahalt bit in the flash_cr1 register. 3. guaranteed by characterization re sults, not tested in production. table 28. oscillator current consumption symbol parameter conditions typ max (1) unit i dd(osc) hse oscillator current consumption (2) quartz or ceramic resonator, cl = 33 pf v dd = 5 v f osc = 24 mhz 1 2.0 (3) ma f osc = 16 mhz 0.6 - f osc = 8 mhz 0.57 - i dd(osc) hse oscillator current consumption (2) quartz or ceramic resonator, cl = 33 pf v dd = 3.3 v f osc = 24 mhz 0.5 1.0 (3) f osc = 16 mhz 0.25 - f osc = 8 mhz 0.18 - 1. during startup, the oscillator current consumption may reach 6 ma. 2. the supply current of the oscillator can be further optimized by selecting a high quality resonator with small r m value. refer to crystal manufacturer for more details 3. informative data. electrical characteristics stm8a f526x/8x/ax stm8af6269/8x/ax 66/125 docid14395 rev 15 table 29. programming current consumption symbol parameter conditions typ max unit i dd(prog) programming current v dd = 5 v, -40 c to 150 c, erasing and programming data or flash program memory 1.0 1.7 ma table 30. typical peripheral current consumption v dd = 5.0 v (1) symbol parameter typ. f master = 2 mhz typ. f master = 16 mhz typ. f master =24 mhz unit i dd(tim1) tim1 supply current (2) 0.03 0.23 0.34 ma i dd(tim2) tim2 supply current (2) 0.02 0.12 0.19 i dd(tim3) tim3 supply current (2) 0.01 0.1 0.16 i dd(tim4) tim4 supply current (2) 0.004 0.03 0.05 i dd(usart) usart supply current (2) 0.03 0.09 0.15 i dd(linuart) linuart supply current (2) 0.03 0.11 0.18 i dd(spi) spi supply current (2) 0.01 0.04 0.07 i dd(i 2 c) i 2 c supply current (2) 0.02 0.06 0.91 i dd(can) can supply current (3) 0.06 0.30 0.40 i dd(awu) awu supply current (2) 0.003 0.02 0.05 i dd(tot_dig) all digital peripherals on 0.22 1 2.4 i dd(adc) adc supply current when converting (4) 0.93 0.95 0.96 1. typical values not tested in production. since the peripheral s are powered by an internally regulated, constant digital supply voltage, the values are sim ilar in the full supply voltage range. 2. data based on a differential i dd measurement between no peripheral clocke d and a single active peripheral. this measurement does not include the pad toggling consumption. 3. data based on a differential idd measurement between rese t configuration (can disabled) and a permanent can data transmit sequence in loopback mode at 1 mhz. this meas urement does not include the pad toggling consumption. 4. data based on a differential i dd measurement between reset configurat ion and continuous a/d conversions. docid14395 rev 15 67/125 stm8af526x/8x/ax stm8af6269/8x/ax electrical characteristics 114 current consumption curves figure 13 to figure 18 show typical current consumption measured with code executing in ram. figure 13. typ. i dd(run)hse vs. v dd @f cpu = 16 mhz, peripherals = on figure 14. typ. i dd(run)hse vs. f cpu @v dd = 5.0 v, peripherals = on 0 1 2 3 4 5 6 7 8 9 10 2.533.544.555.56 v dd [v] i dd(run)hse [ma] 25c 85c 12 5 c 0 1 2 3 4 5 6 7 8 9 10 0 5 10 15 20 25 30 fcpu [mhz] i dd(run)hse [ma] 25c 85c 12 5 c figure 15. typ. i dd(run)hsi vs. v dd @f cpu = 16 mhz, peripherals = off figure 16. typ. i dd(wfi)hse vs. v dd @f cpu = 16 mhz, peripherals = on 0 1 2 3 4 2.5 3.5 4.5 5.5 6.5 vdd [v] idd(run)hsi [ma] 25c 85c 125c 0 1 2 3 4 5 6 2.5 3.5 4.5 5.5 6.5 vdd [v] idd(wfi)hse [ma] 25c 85c 125c figure 17. typ. i dd(wfi)hse vs. f cpu @v dd = 5.0 v, peripherals = on figure 18. typ. i dd(wfi)hsi vs. v dd @f cpu = 16 mhz, peripherals = off 0 1 2 3 4 5 6 0 5 10 15 20 25 30 fcpu [mhz] i dd(wfi)hse [ma] 25c 85c 12 5 c 0 0. 5 1 1. 5 2 2. 5 2.533.544.555.56 v dd [v] i dd(wfi)hsi [ma] 25c 85c 12 5 c electrical characteristics stm8a f526x/8x/ax stm8af6269/8x/ax 68/125 docid14395 rev 15 10.3.3 external clock sources and timing characteristics hse external clock an hse clock can be generated by feeding an external clock signal of up to 24 mhz to the oscin pin. clock characteristics are subject to general operating conditions for v dd and t a . figure 19. hse external clock source hse crystal/ceramic resonator oscillator the hse clock can be supplied using a crystal/ceram ic resonator oscillator of up to 24 mhz. all the information given in this paragraph is based on characterization results with specified typical external components. in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillato r pins in order to mini mize output distortion and startup stabilization time. re fer to the crystal resonator m anufacturer for more details (frequency, package , accuracy...). table 31. hse external clock characteristics symbol parameter conditions min typ max unit f hse_ext user external clock source frequency t a = -40 c to 150 c 0 (1) -24mhz v hsedhl comparator hysteresis - 0.1 x v dd -- v v hseh oscin high-level input pin voltage - 0.7 x v dd -v dd v hsel oscin low-level input pin voltage -v ss - 0.3 x v dd i leak_hse oscin input leakage current v ss < v in < v dd -1 - +1 a 1. if css is used, the external clock must have a frequency above 500 khz. 9 + 6 ( + 9 + 6 ( / ( [ w h u q d o f o r f n v r x u f h 2 6 & , 1 i + 6 ( 6 7 0 0 6 9 docid14395 rev 15 69/125 stm8af526x/8x/ax stm8af6269/8x/ax electrical characteristics 114 figure 20. hse oscilla tor circuit diagram hse oscillator critical g m formula the crystal characteristics have to be checked with the following formula: equation 1 where g mcrit can be calculated with the crystal parameters as follows: equation 2 r m : notional resistance (see crystal specification) l m : notional inductance (see crystal specification) c m : notional capacitance (see crystal specification) co : shunt capacitance (see crystal specification) c l1 = c l2 = c : grounded external capacitance table 32. hse oscillator characteristics symbol parameter conditions min typ max unit r f feedback resistor - - 220 - k c l1 /c l2 (1) recommended load capacitance - - - 20 pf g m oscillator trans conductance - 5 - - ma/v t su(hse) (2) startup time v dd is stabilized -2.8 -ms 1. the oscillator needs two load capacitors, c l1 and c l2 , to act as load for the crystal. the total load capacitance (c load ) is (c l1 * c l2 )/(c l1 + c l2 ). if c l1 = c l2 , c load = c l1/2 . some oscillators have built-in load capacitors, c l1 and c l2 . 2. this value is the startup time, measured from the moment it is enabled (by software) until a stabilized 24 mhz oscillation is reached. it can vary with the crystal type that is used. 0 6 y 9 2 6 & 2 8 7 2 6 & , 1 i + 6 ( w r f r u h & / 5 ) 6 7 0 5 h v r q d w r u & x u u h q w f r q w u r o j p 5 p & p / p 5 h v r q d w r u & / & 2 g m g mcrit ? g mcrit 2 hse f () 2 r m 2co c + () 2 = electrical characteristics stm8a f526x/8x/ax stm8af6269/8x/ax 70/125 docid14395 rev 15 10.3.4 internal clock source s and timing characteristics subject to general operating conditions for v dd and t a . high-speed internal rc oscillator (hsi) figure 21. typical hsi frequency vs v dd table 33. hsi oscillator characteristics symbol parameter conditions min typ max unit f hsi frequency - - 16 - mhz acc hs hsi oscillator user trimming accuracy trimmed by the application for any v dd and t a conditions -1 - 1 % hsi oscillator accuracy (factory calibrated) v dd = 3.0 v v dd 5.5 v, -40 c t a 150 c -5 - 5 t su(hsi) hsi oscillator wakeup time - - - 2 (1) 1. guaranteed by characterization results, not tested in production. s -3% -2% -1% 0% 1% 2% 3% 2.533.544.555.56 v dd [v] hsi frequency variation [%] -40c 25c 85c 125c docid14395 rev 15 71/125 stm8af526x/8x/ax stm8af6269/8x/ax electrical characteristics 114 low-speed internal rc oscillator (lsi) subject to general operating conditions for v dd and t a . figure 22. typical lsi frequency vs v dd table 34. lsi oscillator characteristics symbol parameter conditions min typ max unit f lsi frequency - 112 128 144 khz t su(lsi) lsi oscillator wakeup time - - - 7 (1) 1. guaranteed by characterization re sults, not tested in production. s -3% -2% -1% 0% 1% 2% 3% 2.5 3 3.5 4 4.5 5 5.5 6 v dd [v] lsi frequency variation [%] 25c electrical characteristics stm8a f526x/8x/ax stm8af6269/8x/ax 72/125 docid14395 rev 15 10.3.5 memory characteristics flash program memory/data eeprom memory general conditions: t a = -40 c to 150 c. table 35. flash program memory/data eeprom memory symbol parameter conditions min (1) 1. guaranteed by characterization results, not tested in production. typ max unit v dd operating voltage (all modes, execution/write/erase) f cpu is 16 to 24 mhz with 1 ws f cpu is 0 to 16 mhz with 0 ws 3.0 - 5.5 v v dd operating voltage (code execution) f cpu is 16 to 24 mhz with 1 ws f cpu is 0 to 16 mhz with 0 ws 2.6 - 5.5 t prog standard programming time (including erase) for byte/word/block (1 byte/4 bytes/128 bytes) --66.6 ms fast programming time for 1 block (128 bytes) --33.3 t erase erase time for 1 block (128 bytes) - - 3 3.3 table 36. flash program memory symbol parameter condition min max unit t we temperature for writing and erasing - -40 150 c n we flash program memory endurance (erase/write cycles) (1) 1. the physical granularity of the memory is four byte s, so cycling is performed on four bytes even when a write/erase operation addresses a single byte. t a = 25 c 1000 - cycles t ret data retention time t a = 25 c 40 - years t a = 55 c 20 - docid14395 rev 15 73/125 stm8af526x/8x/ax stm8af6269/8x/ax electrical characteristics 114 table 37. data memory symbol parameter condition min max unit t we temperature for writing and erasing - -40 150 c n we data memory endurance (1) (erase/write cycles) 1. the physical granularity of the memory is four byte s, so cycling is performed on four bytes even when a write/erase operation addresses a single byte. t a = 25 c 300 k - cycles t a = -40c to 125 c 100 k (2) 2. more information on the relationship between data retention time and number of write/erase cycles is available in a separate technical document. - t ret data retention time t a = 25 c 40 (2)(3) 3. retention time for 256b of data memory after up to 1000 cycles at 125 c. - years t a = 55 c 20 (2)(3) - electrical characteristics stm8a f526x/8x/ax stm8af6269/8x/ax 74/125 docid14395 rev 15 10.3.6 i/o port pin characteristics general characteristics subject to general operating conditions for v dd and t a unless otherwise specified. all unused pins must be kept at a fixed voltage, using the output mode of the i/o for example or an external pull-up or pull-down resistor. table 38. i/o static characteristics symbol parameter conditions min typ max unit v il low-level input voltage - -0.3 v 0.3 x v dd v v ih high-level input voltage 0.7 x v dd v dd + 0.3 v v hys hysteresis (1) - 0.1 x v dd - v oh high-level output voltage standard i/0, v dd = 5 v, i = 3 ma v dd - 0.5 v - - standard i/0, v dd = 3 v, i = 1.5 ma v dd - 0.4 v - - v ol low-level output voltage high sink and true open drain i/0, v dd = 5 v i = 8 ma --0.5 v standard i/0, v dd = 5 v i = 3 ma --0.6 standard i/0, v dd = 3 v i = 1.5 ma --0.4 r pu pull-up resistor v dd = 5 v, v in = v ss 35 50 65 k t r , t f rise and fall time (10% - 90%) fast i/os load = 50 pf --35 (2) ns standard and high sink i/os load = 50 pf --125 (2) fast i/os load = 20 pf --20 (2) standard and high sink i/os load = 20 pf --50 (2) i lkg digital input pad leakage current v ss v in v dd --1a i lkg ana analog input pad leakage current v ss v in v dd -40 c < t a < 125 c - - 250 na v ss v in v dd -40 c < t a < 150 c - - 500 i lkg(inj) leakage current in adjacent i/o (3) injection current 4 ma - - 1 (3) a i ddio total current on either v ddio or v ssio including injection currents - - 60 ma 1. hysteresis voltage between schmitt trigger switching levels . guaranteed by characterization results, not tested in production. docid14395 rev 15 75/125 stm8af526x/8x/ax stm8af6269/8x/ax electrical characteristics 114 figure 23. typical v il and v ih vs v dd @ four temperatures figure 24. typical pull-up resistance r pu vs v dd @ four temperatures 2. guaranteed by design. 3. guaranteed by characterization results, not tested in production. 0 1 2 3 4 5 6 2.5 3 3.5 4 4.5 5 5.5 6 v dd [v] v il / v ih [v] -40c 25c 85c 125c 30 35 40 45 50 55 60 2.53 3.544.55 5.56 v dd [v] pull-up resistance [k ohm ] -40c 25c 85c 125c electrical characteristics stm8a f526x/8x/ax stm8af6269/8x/ax 76/125 docid14395 rev 15 figure 25. typical pull-up current i pu vs v dd @ four temperatures (1) 1. the pull-up is a pure resistor (slope goes through 0). typical output level curves figure 26 to figure 35 show typical output level curves measured with output on a single pin. 0 20 40 60 80 100 120 140 0123456 v dd [v] pull-up current [a] -40c 25c 85c 125c figure 26. typ. v ol @ v dd = 3.3 v (standard ports) figure 27. typ. v ol @ v dd = 5.0 v (standard ports) 0 0.25 0.5 0.75 1 1.25 1.5 01234567 i ol [ma] v ol [v] -40c 25c 85c 125c 0 0.25 0.5 0.75 1 1.25 1.5 024681012 i ol [ma] v ol [v] -40c 25c 85c 125c figure 28. typ. v ol @ v dd = 3.3 v (true open drain ports) figure 29. typ. v ol @ v dd = 5.0 v (true open drain ports) 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 02468101214 i ol [ma] v ol [v] -40c 25c 85c 125c 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 0 5 10 15 20 25 i ol [ma] v ol [v] -40c 25c 85c 125c docid14395 rev 15 77/125 stm8af526x/8x/ax stm8af6269/8x/ax electrical characteristics 114 figure 30. typ. v ol @ v dd = 3.3 v (high sink ports) figure 31. typ. v ol @ v dd = 5.0 v (high sink ports) 0 0.25 0.5 0.75 1 1.25 1.5 02468101214 i ol [ma] v ol [v] -40c 25c 85c 125c 0 0.25 0.5 0.75 1 1.25 1.5 0 5 10 15 20 25 i ol [ma] v ol [v] -40c 25c 85c 125c figure 32. typ. v dd - v oh @ v dd = 3.3 v (standard ports) figure 33. typ. v dd - v oh @ v dd = 5.0 v (standard ports) 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 01234567 i oh [ma] v dd - v oh [v] -40c 25c 85c 125c 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 024681012 i oh [ma] v dd - v oh [v] -40c 25c 85c 125c figure 34. typ. v dd - v oh @ v dd = 3.3 v (high sink ports) figure 35. typ. v dd - v oh @ v dd = 5.0 v (high sink ports) 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 02468101214 i oh [ma] v dd - v oh [v] -40c 25c 85c 125c 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 0 5 10 15 20 25 i oh [ma] v dd - v oh [v] -40c 25c 85c 125c electrical characteristics stm8a f526x/8x/ax stm8af6269/8x/ax 78/125 docid14395 rev 15 10.3.7 reset pin characteristics subject to general operating conditions for v dd and t a unless otherwise specified. figure 36. typical nrst v il and v ih vs v dd @ four temperatures table 39. nrst pin characteristics symbol parameter conditions min typ max unit v il(nrst) nrst low-level input voltage (1) 1. guaranteed by characterization re sults, not tested in production. -v ss - 0.3 x v dd v v ih(nrst) nrst high-level input voltage (1) - 0.7 x v dd -v dd v ol(nrst) nrst low-level output voltage (1) i ol = 3 ma - - 0.6 r pu(nrst) nrst pull-up resistor - 30 40 60 k t ifp nrst input filtered pulse (1) -85-315 ns t infp(nrst) nrst input not filtered pulse duration (2) 2. guaranteed by design, not tested in production. -500-- 0 1 2 3 4 5 6 2.5 3 3.5 4 4.5 5 5.5 6 v dd [v] v il / v ih [v] -40c 25c 85c 125c docid14395 rev 15 79/125 stm8af526x/8x/ax stm8af6269/8x/ax electrical characteristics 114 figure 37. typical nrst pull-up resistance r pu vs v dd figure 38. typical nrst pull-up current i pu vs v dd the reset network shown in figure 39 protects the device against parasitic resets. the user must ensure that the level on the nrst pin can go below v il(nrst) max (see table 39: nrst pin characteristics ), otherwise the reset is not taken into account internally. for power consumption sensitive applications, the external reset capacitor value can be reduced to limit the charge/discharge current. if nrst signal is used to reset external circuitry, attention must be ta ken to the charge/discharge time of the external capacitor to fulfill the external devices reset timing condi tions. minimum recomme nded capacity is 10 nf. 30 35 40 45 50 55 60 2.5 3 3.5 4 4.5 5 5.5 6 v dd [v] nrst pull-up resistance [k ohm ] -40c 25c 85c 125c 0 20 40 60 80 100 120 140 0123456 v dd [v] nrst pull-up current [a] -40c 25c 85c 125c electrical characteristics stm8a f526x/8x/ax stm8af6269/8x/ax 80/125 docid14395 rev 15 figure 39. recommended reset pin protection 10.3.8 tim 1, 2, 3, and 4 electrical specifications subject to general operating conditions for v dd , f master and t a . 0 6 y 9 ( [ w h u q d o u h v h w f l u f x l w ) 1 5 6 7 ) l o w h u 6 7 0 $ 2 s w l r q d o 9 ' ' 5 3 8 , q w h u q d o u h v h w table 40. tim 1, 2, 3, and 4 electrical specifications symbol parameter conditions min typ max unit f ext timer external clock frequency (1) 1. not tested in production. ---24mhz docid14395 rev 15 81/125 stm8af526x/8x/ax stm8af6269/8x/ax electrical characteristics 114 10.3.9 spi interface unless otherwise specified, the parameters given in table 41 are derived from tests performed under ambient temperature, f master frequency, and v dd supply voltage conditions. t master = 1/f master . refer to i/o port characteristics for more de tails on the input/output alternate function characteristics (nss, sck, mosi, miso). table 41. spi characteristics symbol parameter conditions min max unit f sck 1/t c(sck) spi clock frequency master mode 0 10 mhz slave mode v dd < 4.5 v 0 6 (1) v dd = 4.5 v to 5.5 v 0 8 (1) t r(sck) t f(sck) spi clock rise and fall time capacitive load: c = 30 pf - 25 (2) ns t su(nss) (3) nss setup time slave mode 4 * t master - t h(nss) (3) nss hold time slave mode 70 - t w(sckh) (3) t w(sckl) (3) sck high and low time master mode t sck /2 - 15 t sck /2 + 15 t w(sckh) (3) t w(sckl) (3) t su(mi) (3) t su(si) (3) data input setup time master mode 5 - slave mode 5 - t h(mi) (3) t h(si) (3) data input hold time master mode 7 - slave mode 10 - t a(so) (3)(4) data output access time slave mode - 3* t master t dis(so) (3)(5) data output disable time slave mode 25 t v(so) (3) data output valid time slave mode (after enable edge) v dd < 4.5 v - 75 v dd = 4.5 v to 5.5 v - 53 t v(mo) (3) data output valid time master mode (after enable edge) - 30 t h(so) (3) data output hold time slave mode (after enable edge) 31 - t h(mo) (3) master mode (after enable edge) 12 - 1. f sck < f master /2. 2. the pad has to be configured accordingly (fast mode). 3. guaranteed by design or by characteri zation results, not tested in production. 4. min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 5. min time is for the minimum time to invalidate the output and th e max time is for the maximum time to put the data in hi-z. electrical characteristics stm8a f526x/8x/ax stm8af6269/8x/ax 82/125 docid14395 rev 15 figure 40. spi timing diagram in slave mode and with cpha = 0 1. measurement points are at cmos levels: 0.3 v dd and 0.7 v dd . figure 41. spi timing diagram in slave mode and with cpha = 1 1. measurement points are at cmos levels: 0.3 v dd and 0.7 v dd . d l f 6 & . , q s x w 1 6 6 l q s x w w 6 8 1 6 6 w f 6 & . w k 1 6 6 & 3 + $ & 3 2 / & 3 + $ & 3 2 / w z 6 & . + w z 6 & . / w 9 6 2 w k 6 2 w u 6 & . w i 6 & . w g l v 6 2 w d 6 2 0 , 6 2 2 8 7 3 8 7 0 2 6 , , 1 3 8 7 0 6 % 2 8 7 % , 7 2 8 7 / 6 % 2 8 7 w v x 6 , w k 6 , 0 6 % , 1 % , 7 , 1 / 6 % , 1 d l e 1 6 6 l q s x w w 6 8 1 6 6 w f 6 & . w k 1 6 6 6 & . l q s x w & 3 + $ & 3 2 / & 3 + $ & 3 2 / w z 6 & . + w z 6 & . / w d 6 2 w y 6 2 w k 6 2 w u 6 & . w i 6 & . w g l v 6 2 0 , 6 2 2 8 7 3 8 7 0 2 6 , , 1 3 8 7 w v x 6 , w k 6 , 0 6 % 2 8 7 0 6 % , 1 % , 7 2 8 7 / 6 % 2 8 7 / 6 % , 1 % , 7 , 1 docid14395 rev 15 83/125 stm8af526x/8x/ax stm8af6269/8x/ax electrical characteristics 114 figure 42. spi timing diagram - master mode 1. measurement points are at cmos levels: 0.3 v dd and 0.7 v dd . d l f 6 & . 2 x w s x w & 3 + $ 0 2 6 , 2 8 7 3 8 7 0 , 6 2 , 1 3 8 7 & 3 + $ / 6 % 2 8 7 / 6 % , 1 & 3 2 / & 3 2 / % , 7 2 8 7 1 6 6 l q s x w w f 6 & . w z 6 & . + w z 6 & . / w u 6 & . w i 6 & . w k 0 , + l j k 6 & . 2 x w s x w & 3 + $ & 3 + $ & 3 2 / & 3 2 / w v x 0 , w y 0 2 w k 0 2 0 6 % , 1 % , 7 , 1 0 6 % 2 8 7 electrical characteristics stm8a f526x/8x/ax stm8af6269/8x/ax 84/125 docid14395 rev 15 10.3.10 i 2 c interface characteristics table 42. i 2 c characteristics symbol parameter standard mode i 2 cfast mode i 2 c (1) unit min (2) max (2) min (2) max (2) t w(scll) scl clock low time 4.7 - 1.3 - s t w(sclh) scl clock high time 4.0 - 0.6 - t su(sda) sda setup time 250 - 100 - ns t h(sda) sda data hold time 0 (3) -0 (4) 900 (3) t r(sda) t r(scl) sda and scl rise time (v dd 3 v to 5.5 v) - 1000 - 300 t f(sda) t f(scl) sda and scl fall time (v dd 3 v to 5.5 v) - 300 - 300 t h(sta) start condition hold time 4.0 - 0.6 - s t su(sta) repeated start condition setup time 4.7 - 0.6 - t su(sto) stop condition setup time 4.0 - 0.6 - s t w(sto:sta) stop to start condition time (bus free) 4.7 - 1.3 - s c b capacitive load for each bus line - 400 - 400 pf 1. f master , must be at least 8 mhz to achieve max fast i 2 c speed (400 khz) 2. data based on standard i 2 c protocol requirement, not tested in production 3. the maximum hold time of the start condition has only to be met if the interface does not stretch the low time 4. the device must internally provide a hold time of at least 300 ns for the sda signal in order to bridge the undefined region of the falling edge of scl docid14395 rev 15 85/125 stm8af526x/8x/ax stm8af6269/8x/ax electrical characteristics 114 10.3.11 10-bit adc characteristics subject to general operating conditions for v dda , f master and t a unless otherwise specified. figure 43. typical application with adc 1. legend: r ain = external resistance, c ain = capacitors, c samp = internal sample and hold capacitor. table 43. adc characteristics symbol parameter conditions min typ max unit f adc adc clock frequency - 111 khz - 4 mhz khz/mhz v dda analog supply - 3 - 5.5 v v ref+ positive reference voltage - 2.75 - v dda v ref- negative reference voltage - v ssa -0.5 v ain conversion voltage range (1) 1. during the sample time, the sampling capacitance, c samp (3 pf typ), can be charged/discharged by the external source. the internal resistance of the analog so urce must allow the capacitance to reach its final voltage level within t s. after the end of the sample time t s , changes of the analog input voltage have no effect on the conversion result. -v ssa -v dda devices with external v ref+ / v ref- pins v ref- -v ref+ c samp internal sample and hold capacitor - - - 3 pf t s (1) sampling time (3 x 1/f adc ) f adc = 2 mhz - 1.5 - s f adc = 4 mhz - 0.75 - t stab wakeup time from standby f adc = 2 mhz - 7 - f adc = 4 mhz - 3.5 - t conv total conversion time including sampling time (14 x 1/f adc ) f adc = 2 mhz - 7 - f adc = 4 mhz - 3.5 - r switch equivalent switch resistance - - - 30 k 0 6 y 9 ^ d d? 5 $ , 1 & $ , 1 9 $ , 1 / e? s 9 7 9 9 7 9 & v d p s , / e l w $ ' f r q y h u v l r q 5 v z l w f k 7 v electrical characteristics stm8a f526x/8x/ax stm8af6269/8x/ax 86/125 docid14395 rev 15 figure 44. adc accuracy characteristics 1. example of an actual transfer curve 2. the ideal transfer curve 3. end point correlation line e t = total unadjusted error: maximum deviation betw een the actual and the ideal transfer curves. e o = offset error: deviation between the fi rst actual transition and the first ideal one. e g = gain error: deviation between the last ideal transition and the last actual one. e d = differential linearity error: maximum deviation between actual steps and the ideal one. e l = integral linearity error: maximum deviation between any actual transition an d the end point correlation line. table 44. adc accuracy for v dda = 5 v symbol parameter conditions typ max (1) 1. guaranteed by characterization re sults, not tested in production. unit |e t | total unadjusted error (2) 2. adc accuracy vs. injection current: any positive or negat ive injection current within the limits specified for i inj(pin) and i inj(pin) in section 10.3.6 does not affect the adc accuracy. f adc = 2 mhz 1.4 3 (3) 3. tue 2lsb can be reached on specific sale s types on the whole temperature range. lsb |e o | offset error (2) 0.8 3 |e g | gain error (2) 0.1 2 |e d | differential linearity error (2) 0.9 1 |e l | integral linearity error (2) 0.7 1.5 |e t | total unadjusted error (2) f adc = 4 mhz 1.9 (4) 4. target values. 4 (4) |e o | offset error (2) 1.3 (4) 4 (4) |e g | gain error (2) 0.6 (4) 3 (4) |e d | differential linearity error (2) 1.5 (4) 2 (4) |e l | integral linearity error (2) 1.2 (4) 1.5 (4) e o e g 1lsb ideal 1lsb ideal v dda v ssa ? 1024 ---------------------------------------- - = 1023 1022 1021 5 4 3 2 1 0 7 6 1234567 1021102210231024 (1) (2) e t e d e l (3) v dda v ssa docid14395 rev 15 87/125 stm8af526x/8x/ax stm8af6269/8x/ax electrical characteristics 114 10.3.12 emc characteristics susceptibility tests are perfor med on a sample basis during product characterization. functional ems (electromagnetic susceptibility) while executing a simple application (toggling 2 leds through i/o ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the leds). ? esd : electrostatic discharge (positive and negati ve) is applied on all pins of the device until a functional disturbance occurs. th is test conforms with the iec 1000-4-2 standard. ? ftb : a burst of fast transient voltage (p ositive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a function al disturbance occurs. this test conforms with the iec 1000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in the table below based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are per formed at component level with a typical application environment and simplified mcu soft ware. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in re lation with the emc level requested for his application. software recommendations the software flowchart must include the m anagement of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) prequalification trials most of the common failures (unexpected reset and program counter corruption) can be recovered by applying a low state on the nr st pin or the oscillato r pins for 1 second. to complete these trials, esd stress can be applie d directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). table 45. ems data symbol parameter conditions level/class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3 v, t a = 25 c, f master = 16 mhz (hsi clock), conforms to iec 1000-4-2 3/b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3 v, t a = 25 c, f master = 16 mhz (hsi clock), conforms to iec 1000-4-4 4/a electrical characteristics stm8a f526x/8x/ax stm8af6269/8x/ax 88/125 docid14395 rev 15 electromagnetic interference (emi) emission tests conform to the iec 61967-2 standard for test software, board layout and pin loading. absolute maximum ratings (electrical sensitivity) based on two different tests (esd and lu) using specific measurement methods, the product is stressed to determine its performance in terms of electrical sensitivity. for more details, refer to the application note an1181. electrostatic discharge (esd) electrostatic discharges (3 positive then 3 negative pulses separated by 1 second) are applied to the pins of each sample according to each pin combinati on. the sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). this test conforms to the jesd22-a114a/a115a standard. for more details, refer to the application note an1181. table 46. emi data symbol parameter conditions unit general conditions monitored frequency band max f cpu (1) 1. guaranteed by characterization re sults, not tested in production. 8 mhz 16 mhz 24 mhz s emi peak level v dd = 5 v, t a = 25 c, lqfp80 package conforming to iec 61967-2 0.1 mhz to 30 mhz 15 17 22 dbv 30 mhz to 130 mhz 18 22 16 130 mhz to 1 ghz -1 3 5 emi level - 2 2.5 2.5 table 47. esd absolute maximum ratings symbol ratings conditions class maximum value (1) 1. guaranteed by characterization results, not tested in production unit v esd(hbm) electrostatic discharge voltage (human body model) t a = 25 c, conforming to jesd22-a114 3a 4000 v v esd(cdm) electrostatic discharge voltage (charge device model) t a = 25 c, conforming to jesd22-c101 3 500 v esd(mm) electrostatic discharge voltage (charge device model) t a = 25 c, conforming to jesd22-a115 b 200 docid14395 rev 15 89/125 stm8af526x/8x/ax stm8af6269/8x/ax electrical characteristics 114 static latch-up two complementary static tests are required on 10 parts to assess the latch-up performance. ? a supply overvoltage (applied to each power supply pin) and ? a current injection (applied to each input, output and configurable i/o pin) are performed on each sample. this test conforms to the eia/jesd 78 ic la tch-up standard. for more details, refer to the application note an1181. table 48. electrical sensitivities symbol parameter conditions class (1) 1. class description: a class is an stmi croelectronics internal specification. all its limits are higher than the jedec specifications, that means when a device belongs to class a it exceeds the jedec standard. b class strictly covers all the jede c criteria (international standard). lu static latch-up class t a = 25 c a t a = 85 c t a = 125 c t a = 150 c package information stm8af526x/8x/ax stm8af6269/8x/ax 90/125 docid14395 rev 15 11 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. 11.1 lqfp80 package information figure 45. lqfp80 - 80-pin, 14 x 14 mm low-profile quad flat package outline 1. drawing is not to scale. b $ $ $ % % % ) $ % . 4 ) & ) # ! 4 ) / . 0 ) . , , k c # 3 % ! 4 ) . ' 0 , ! . % ' ! 5 ' % 0 , ! . % m m # c c c ! ! ! 3 ? - % e ! docid14395 rev 15 91/125 stm8af526x/8x/ax stm8af6269/8x/ax package information 114 table 49. lqfp80 - 80-pin, 14 x 14 mm low-profile quad flat package mechanical data (1) 1. values in inches are converted fr om mm and rounded to 4 decimal digits. symbol millimeters inches min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.220 0.320 0.380 0. 0087 0.0126 0.0150 c 0.090 - 0.200 0.0035 - 0.0079 d 15.800 16.000 16.200 0.6220 0.6299 0.6378 d1 13.800 14.000 14.200 0.5433 0.5512 0.5591 d3 - 12.350 - - 0.4862 - e 15.800 16.000 16.200 0.6220 0.6299 0.6378 e1 13.800 14.000 14.200 0.5433 0.5512 0.5591 e3 - 12.350 - - 0.4862 - e - 0.650 - - 0.0256 - l 0.450 0.600 0.750 0. 0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - k 03.57 03.57 ccc - - 0.100 - - 0.0039 package information stm8af526x/8x/ax stm8af6269/8x/ax 92/125 docid14395 rev 15 figure 46. lqfp80 - 80-pin, 14 x 14 mm low-profile quad flat package recommended footprint 1. dimensions are expr essed in millimeters. 4 @ ' 1 docid14395 rev 15 93/125 stm8af526x/8x/ax stm8af6269/8x/ax package information 114 device marking the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. figure 47. lqfp80 marking example (package top view) 1. parts marked as "es","e? or accompanied by an engi neering sample notification letter are not yet qualified and therefore not approved for use in production. st is not responsible for any consequences resulting from such use. in no event will st be liable for t he customer using any of these engineering samples in production. st's quality department must be contacted to run a qualification activity prior to any decision to use these engineering samples. 3 u r g x f w l g h q w l i l f d w l r q 3 l q l g h q w l i l h u 5 h y l v l r q f r g h ' d w h f r g h : 8 8 6 w d q g d u g 6 7 o r j r 9 9 9 9 9 9 9 9 9 9 0 6 9 package information stm8af526x/8x/ax stm8af6269/8x/ax 94/125 docid14395 rev 15 11.2 lqfp64 package information figure 48. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat package outline 1. drawing is not to scale. table 50. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d - 12.000 - - 0.4724 - d1 - 10.000 - - 0.3937 - d3 - 7.500 - - 0.2953 - e - 12.000 - - 0.4724 - e1 - 10.000 - - 0.3937 - : b 0 ( b 9 $ $ $ 6 ( $ 7 , 1 * 3 / $ 1 ( f f f & e & f $ / / . , ' ( 1 7 , ) , & $ 7 , 2 1 3 , 1 ' ' ' h ( ( ( * $ 8 * ( 3 / $ 1 ( p p docid14395 rev 15 95/125 stm8af526x/8x/ax stm8af6269/8x/ax package information 114 figure 49. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat package recommended footprint 1. dimensions are expr essed in millimeters. e3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - k 03.57 03.57 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. table 50. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max a i c package information stm8af526x/8x/ax stm8af6269/8x/ax 96/125 docid14395 rev 15 device marking the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. figure 50. lqfp64 marking example (package top view) 1. parts marked as "es","e? or accompanied by an engi neering sample notification letter are not yet qualified and therefore not approved for use in production. st is not responsible for any consequences resulting from such use. in no event will st be liable for t he customer using any of these engineering samples in production. st's quality department must be contacted to run a qualification activity prior to any decision to use these engineering samples. 0 6 9 3 u r g x f w l g h q w l i l f d w l r q 3 l q l g h q w l i l h u 5 h y l v l r q f r g h ' d w h f r g h : 8 8 6 w d q g d u g 6 7 o r j r 9 9 9 9 9 9 9 9 9 9 docid14395 rev 15 97/125 stm8af526x/8x/ax stm8af6269/8x/ax package information 114 11.3 lqfp48 package information figure 51. lqfp48 - 48-pin, 7 x 7 mm low-profile quad flat package outline 1. drawing is not to scale. " ? - % ? 6 0 ) . ) $ % . 4 ) & ) # ! 4 ) / . c c c # # $ m m ' ! 5 ' % 0 , ! . % b ! ! ! c ! , , $ $ % % % e 3 % ! 4 ) . ' 0 , ! . % + package information stm8af526x/8x/ax stm8af6269/8x/ax 98/125 docid14395 rev 15 table 51. lqfp48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d 8.800 9.000 9.200 0.3465 0.3543 0.3622 d1 6.800 7.000 7.200 0.2677 0.2756 0.2835 d3 - 5.500 - - 0.2165 - e 8.800 9.000 9.200 0.3465 0.3543 0.3622 e1 6.800 7.000 7.200 0.2677 0.2756 0.2835 e3 - 5.500 - - 0.2165 - e - 0.500 - - 0.0197 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - k 03.57 03.57 ccc - - 0.080 - - 0.0031 docid14395 rev 15 99/125 stm8af526x/8x/ax stm8af6269/8x/ax package information 114 figure 52. lqfp48 - 48-pin, 7 x 7 mm low-profile quad flat package recommended footprint 1. dimensions are expr essed in millimeters. device marking the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. a i d package information stm8af526x/8x/ax stm8af6269/8x/ax 100/125 docid14395 rev 15 figure 53. lqfp48 marking example (package top view) 1. parts marked as "es","e? or accompanied by an engi neering sample notification letter are not yet qualified and therefore not approved for use in production. st is not responsible for any consequences resulting from such use. in no event will st be liable for t he customer using any of these engineering samples in production. st's quality department must be contacted to run a qualification activity prior to any decision to use these engineering samples. 0 6 9 3 u r g x f w l g h q w l i l f d w l r q 3 l q l g h q w l i l h u 5 h y l v l r q f r g h ' d w h f r g h : 8 8 6 w d q g d u g 6 7 o r j r 9 9 9 9 9 9 9 9 9 9 docid14395 rev 15 101/125 stm8af526x/8x/ax stm8af6269/8x/ax package information 114 11.4 lqfp32 package information figure 54. lqfp32 - 32-pin, 7 x 7 mm low-profile quad flat package outline 1. drawing is not to scale. $ $ $ % % % ! , , + ! ! ! c b ' ! 5 ' % 0 , ! . % m m 3 % ! 4 ) . ' 0 , ! . % # 0 ) . ) $ % . 4 ) & ) # ! 4 ) / . c c c # 7 @ . & @ 7 e package information stm8af526x/8x/ax stm8af6269/8x/ax 102/125 docid14395 rev 15 table 52. lqfp32 - 32-pin, 7 x 7 mm low-profile quad flat package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.300 0.370 0.450 0.0118 0.0146 0.0177 c 0.090 - 0.200 0.0035 - 0.0079 d 8.800 9.000 9.200 0.3465 0.3543 0.3622 d1 6.800 7.000 7.200 0.2677 0.2756 0.2835 d3 - 5.600 - - 0.2205 - e 8.800 9.000 9.200 0.3465 0.3543 0.3622 e1 6.800 7.000 7.200 0.2677 0.2756 0.2835 e3 - 5.600 - - 0.2205 - e - 0.800 - - 0.0315 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - k 03.57 03.57 ccc - - 0.100 - - 0.0039 docid14395 rev 15 103/125 stm8af526x/8x/ax stm8af6269/8x/ax package information 114 figure 55. lqfp32 - 32-pin, 7 x 7 mm low-profile quad flat package recommended footprint 1. dimensions are expr essed in millimeters. 6 ? & 0 ? 6 package information stm8af526x/8x/ax stm8af6269/8x/ax 104/125 docid14395 rev 15 device marking the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. figure 56. lqfp32 marking example (package top view) 1. parts marked as "es","e? or accompanied by an engi neering sample notification letter are not yet qualified and therefore not approved for use in production. st is not responsible for any consequences resulting from such use. in no event will st be liable for t he customer using any of these engineering samples in production. st's quality department must be contacted to run a qualification activity prior to any decision to use these engineering samples. 0 6 9 3 u r g x f w l g h q w l i l f d w l r q 3 l q l g h q w l i l h u 5 h y l v l r q f r g h ' d w h f r g h : 8 8 6 w d q g d u g 6 7 o r j r 9 9 9 9 9 9 9 9 9 9 docid14395 rev 15 105/125 stm8af526x/8x/ax stm8af6269/8x/ax package information 114 11.5 vfqfpn32 package information figure 57. vfqfpn32 - 32-pin, 5x5 mm, 0.5 mm pitch very thin profile fine pitch quad flat package outline 1. drawing is not to scale. ? - % ? ! - + / 2 ? 6 6 h d w l q j s o d q h g g g & & $ $ $ ' h 3 l q , ' 5 ( / / ' e ( % r w w r p y l h z package information stm8af526x/8x/ax stm8af6269/8x/ax 106/125 docid14395 rev 15 table 53. vfqfpn32 - 32-pin, 5 x 5 mm, 0.5 mm pitch very thin profile fine pitch quad flat package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 0.800 0.900 1.000 0.0315 0.0354 0.0394 a1 0.000 0.020 0.050 0.0000 0.0008 0.0020 a3 - 0.200 - - 0.0079 - b 0.180 0.250 0.300 0.0071 0.0098 0.0118 d 4.850 5.000 5.150 0.1909 0.1969 0.2028 d2 3.500 3.600 3.700 0.1378 0.1417 0.1457 e 4.850 5.000 5.150 0.1909 0.1969 0.2028 e2 3.500 3.600 3.700 0.1378 0.1417 0.1457 e - 0.500 - - 0.0197 - l 0.300 0.400 0.500 0.0118 0.0157 0.0197 ddd - - 0.050 - - 0.0020 docid14395 rev 15 107/125 stm8af526x/8x/ax stm8af6269/8x/ax package information 114 figure 58. vfqfpn32 - 32-pin, 5 x 5 mm, 0.5 mm pitch very thin profile fine pitch quad flat package recommended footprint 1. dimensions are expr essed in millimeters. ? & 0 ? ! - + / 2 ? 6 9 d u $ 9 d u % 9 d u $ 9 d u % package information stm8af526x/8x/ax stm8af6269/8x/ax 108/125 docid14395 rev 15 device marking the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. figure 59. vfqfpn32 marking example (package top view) 1. parts marked as "es","e? or accompanied by an engi neering sample notification letter are not yet qualified and therefore not approved for use in production. st is not responsible for any consequences resulting from such use. in no event will st be liable for t he customer using any of these engineering samples in production. st's quality department must be contacted to run a qualification activity prior to any decision to use these engineering samples. 0 6 9 3 u r g x f w l g h q w l i l f d w l r q 3 l q l g h q w l i l h u 5 h y l v l r q f r g h ' d w h f r g h : 8 8 6 w d q g d u g 6 7 o r j r 9 9 9 9 9 9 docid14395 rev 15 109/125 stm8af526x/8x/ax stm8af6269/8x/ax package information 114 11.6 thermal characteristics in case the maximum chip junction temperature (t jmax ) specified in table 24: general operating conditions is exceeded, the func tionality of the device cannot be guaranteed. t jmax , in degrees celsius, may be calculated using the following equation: t jmax = t amax + (p dmax x ja ) where: t amax is the maximum ambient temperature in c ja is the package junction-to-ambient thermal resistance in c/w p dmax is the sum of p intmax and p i/omax (p dmax = p intmax + p i/omax ) p intmax is the product of i dd and v dd , expressed in watts. this is the maximum chip internal power. p i/omax represents the maximum power dissipation on output pins where: p i/omax = (v ol * i ol ) + ((v dd - v oh ) * i oh ) taking into account the actual v ol / i ol and v oh / i oh of the i/os at low- and high-level in the application. 11.6.1 reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). available from www.jedec.org. table 54. thermal characteristics (1) 1. thermal resistances are based on jedec jesd51- 2 with 4-layer pcb in a natural convection environment. symbol parameter value unit ja thermal resistance junction-ambient lqfp 80 - 14 x 14 mm 38 c/w thermal resistance junction-ambient lqfp 64 - 10 x 10 mm 46 thermal resistance junction-ambient lqfp 48 - 7 x 7 mm 57 thermal resistance junction-ambient lqfp 32 - 7 x 7 mm 59 thermal resistance junction-ambient vfqfpn 32 - 5 x 5 mm 25 package information stm8af526x/8x/ax stm8af6269/8x/ax 110/125 docid14395 rev 15 11.6.2 selecting the product temperature range when ordering the microcontroller, the temperature range is specified in the order code (see figure 60: stm8af526x/8x/ax and stm8af6269/8x/ax ordering information scheme1 on page 111 ). the following example shows how to calculate the temperature range needed for a given application. assuming the following ap plication conditions: ? maximum ambient temperature t amax = 82 c (measured according to jesd51-2) ?i ddmax = 8 ma ?v dd = 5 v ? maximum 20 i/os used at the same time in output at low-level with i ol = 8 ma ?v ol = 0.4 v p intmax = 8 ma x 5 v = 400 mw p iomax = 20 x 8 ma x 0.4 v = 64 mw this gives: p intmax = 400 mw and p iomax 64 mw p dmax = 400 mw + 64 mw thus: p dmax = 464 mw. using the values obtained in table 54: thermal characteristics t jmax is calculated as follows: for lqfp64 46 c/w t jmax = 82 c + (46 c/w x 464 mw) = 82 c + 21 c = 103 c this is within the range of the suffix c version parts (-40 c < t j < 125 c). parts must be ordered at least with the temperature range suffix c. docid14395 rev 15 111/125 stm8af526x/8x/ax stm8af6269/8x/ax ordering information 114 12 ordering information figure 60. stm8af526x/8x/ax and stm8af6 269/8x/ax ordering information scheme 1 1. for a list of available options (e.g. memory size, package) and orderable part numbers or for further information on any aspect of this device, please go to www.st.com or contact the nearest st sales office. 2. qualified and characterized according to aec q100 and q003 or equivalent, advanced screening according to aec q001 and q002 or equivalent. 3. customer specific fastrom code or custom device configuration. this field shows ?sss? if the device contains a super set sili con, usually equipped with bigger memory and more i/os. this silicon is supposed to be replaced later by the target silicon. stm8a 2 f62aatdxxx 3 y product class 8-bit automotive microcontroller program memory size 6 = 32 kbyte 8 = 64 kbyte a= 128 kbyte package type t = lqfp u = vfqfpn example: device family 52 = silicon rev u and rev t, can/lin 62 = silicon rev u and rev t, lin only program memory type f = flash + eeprom p = fastrom temperature range a = -40 to 85 c c = -40 to 125 c d = -40 to 150 c pin count 6 = 32 pins 8 = 48 pins 9 = 64 pins a = 80 pins packing y = tray u = tube x = tape and reel compliant with eia 481-c stm8 development tools stm8af526x/8x/ax stm8af6269/8x/ax 112/125 docid14395 rev 15 13 stm8 development tools development tools for the stm8a microcontrollers include the ? stice emulation system offeri ng tracing and code profiling ? stvd high-level language debugger including assembler and visual development environment - seamless integration of third party c compilers ? stvp flash programming software in addition, the stm8a comes with starter kits , evaluation boards and low-cost in-circuit debugging/programming tools. 13.1 emulation and in-c ircuit debugging tools the stm8 tool line includes the stice emul ation system offering a complete range of emulation and in-circuit debugging features on a platform that is desi gned for versatility and cost-effectiveness. in addition, stm8a application development is supported by a low-cost in-circuit debugger/programmer. the stice is the fourth generation of full-fe atured emulators from stmicroelectronics. it offers new advanced debugging capabilities including tracin g, profiling and code coverage analysis to help detect execution bottlenecks and dead code. in addition, stice offers in-circuit debuggi ng and programming of stm8a microcontrollers via the stm8 single wire interface module (swim), which allows non-intrusive debugging of an application while it runs on the target microcontroller. for improved cost effectiveness, stice is bas ed on a modular design that allows users to order exactly what they need to meet their development requirements and to adapt their emulation system to support existing and future st microcontrollers. 13.1.1 stice key features ? program and data trace recording up to 128 k records ? advanced breakpoints with up to 4 levels of conditions ? data breakpoints ? real-time read/write of all device resources during emulation ? occurrence and time profiling and code coverage analysis (new features) ? in-circuit debugging/prog ramming via swim protocol ? 8-bit probe analyzer ? 1 input and 2 output triggers ? usb 2.0 high-speed interface to host pc ? power supply follower managing application voltages between 1.62 to 5.5 v ? modularity that allows users to specify the components they need to meet their development requirements and adapt to future requirements ? supported by free software tools that include integrated development environment (ide), programming software interface and assembler for stm8. docid14395 rev 15 113/125 stm8af526x/8x/ax stm8af6269/8x/ax stm8 development tools 114 13.2 software tools stm8 development tools are supported by a complete, free software package from stmi- croelectronics that includes st visual devel op (stvd) ide and the st visual programmer (stvp) software interface. st vd provides seamless integration of the cosmic and raiso- nance c compilers for stm8. 13.2.1 stm8 toolset the stm8 toolset with stvd integrated development environment and stvp programming software is available for free download at www.st.com . this package includes: st visual develop full-featured integrated development environment from stmicroelectronics, featuring: ? seamless integration of c and asm toolsets ? full-featured debugger ? project management ? syntax highlighting editor ? integrated programming interface ? support of advanced emulatio n features for stice such as code profiling and coverage st visual programmer (stvp) easy-to-use, unlimited graphical interface allowi ng read, write and verification of the stm8a microcontroller?s flash memory. stvp also of fers project mode for saving programming configurations and automating programming sequences. 13.2.2 c and assembly toolchains control of c and assembly toolchains is seam lessly integrat ed into the stvd integrated development environment, making it possible to configure and control the building of the application directly from an easy-to-use graphi cal interface. available toolchains include: c compiler for stm8 all compilers are available in free version with a limited code size depending on the compiler. for more information, refer to ww w.cosmic-software.com, www.raisonance.com, and www.iar.com. stm8 assembler linker free assembly toolchain included in the stm8 toolset, which allows users to assemble and link their application source code. stm8 development tools stm8af526x/8x/ax stm8af6269/8x/ax 114/125 docid14395 rev 15 13.3 programming tools during the development cycle, stice provides in-circuit pr ogramming of the stm8a flash microcontroller on the application board via th e swim protocol. additional tools are to include a low-cost in-circuit programmer as well as st socket boards, which provide dedicated programming platforms with sockets for programming the stm8a. for production environments, programmers will include a comp lete range of gang and automated programming solutions from thir d-party tool developers already supplying programmers for the stm8 family. docid14395 rev 15 115/125 stm8af526x/8x/ax stm8af6269/8x/ax revision history 124 14 revision history table 55. document revision history date revision changes 31-jan-2008 1 initial release 22-aug-2008 2 added ?h? products to the datasheet (flash no eeprom). section : features on cover page: updated memories, reset and supply management, communication interfaces and i/os; reduced wakeup pins by 1. table 1: device summary : removed stm8af6168, stm8af6148, stm8af6166, stm8af6146, stm8af5168, stm8af5186, stm8af5176, and stm8af5166. section 1: introduction , section 5: product overview , section 9: option bytes , section 6.2: alternate function remapping , table 21: current characteristics : updated reference documentation: rm0009, pm0047, and um0470. section 2: description : added information about peak performance. section 3: product line-up : removed stm8a common features table. table 4: peripheral clock gating bits (clk_pckenr1) : removed stm8af5186t, stm8af5176t, stm8af5168t, and stm8af5166t. table 5: peripheral clock gating bits (clk_pckenr2) : removed stm8af6168t, stm8af6166t, stm8af6148t, and stm8af6146t. section 5: product overview : made minor content changes and improved readability and layout. section 5.5.3: 128 khz low-speed internal rc oscillator (lsi) : major modification, tmu included. section 5.5.2: 16 mhz high-speed internal rc oscillator (hsi) : user trimming updated. section 5.5.3: 128 khz low-speed internal rc oscillator (lsi) : lsi as cpu clock added. section 5.5.4: 24 mhz high-speed external crystal oscillator (hse) , section 5.5.5: external clock input : maximum frequency conditional 32 kbyte/128 kbyte. section 5.8: analog to digital converter (adc) : scan for 128 kbyte removed. section 5.9: communication interfaces , section 5.9.3: serial peripheral interface (spi) : spi 10 mb/s. figure 3: lqfp 80-pin pinout , figure 4: lqfp 64-pin pinout , figure 6: stm8af62xx lqfp/vfqfpn 32-pin pinout : amended footnote 1. table 12: memory model 128k : hs output changed from 20 ma to 8 ma. section 7: memory and register map : corrected table 8: register and memory map ; removed address list; added table 14: general hardware register map . section 10.3.2: supply current characteristics note on typical/wc values added. revision history stm8af526x/8x/ax stm8af6269/8x/ax 116/125 docid14395 rev 15 22-aug-2008 2 (continued) table 18: typ. idd(wfi)hsi vs . vdd @ fcpu = 16 mhz, peripherals = off : replaced the source blocks ?simple usart?, ?very low-end timer (timer 4)?, and ?eeprom? with ?linuart?, ?timer4? and ?reserved? respectively, added tmu registers. table 20: hse oscillator circuit diagram : updated opt6 and nopt6, added opt7 to 17 (tmu, bl) table 21: typical hsi frequency vs vdd : updated opt1 ubc[7:0], opt4 ckawusel, opt4 prsc [1:0], and opt6, added opt7 to 16 (tmu). table 23: operating lifetime : amended footnotes. table 26: total current consumption in run, wait and slow mode. general conditions for vdd apply, ta = -40 c to 150 c : added parameter ?voltage and current operating conditions?. table 27: total current consumption in halt and active-halt modes. general conditions for vdd applied. ta = -40 c to 55 c unless otherwise stated : amended footnotes. table 28: oscillator current consumption : replaced. table 29: programming current consumption : amended maximum data and footnotes. table 21: current characteristics : replaced. table 22: thermal characteristics : added and amended i dd(run) data; amended i dd(wfi) data; amended footnotes. table 32: hse oscillator characteristics : filled in, amended maximum data and footnotes. figure 13 to figure 18 : info on peripheral activity added. table 33: hsi oscillator characteristics : modified f hse_ext data and added v hsedhl data. table 35: flash program memory/data eeprom memory : removed acc hsi parameters and replaced with acc hs parameters; amended data and footnotes. amended data of ? ram and hardware registers ? table. table 37: data memory : updated names and data of n rw and t ret parameters. table 40: tim 1, 2, 3, and 4 electrical specifications : added v oh and v ol parameters; updated i lkg ana parameter. removed: output driving current (standard ports), output driving current (true open drain ports) , and output driving current (high sink ports). table 46: emi data : updated f adc , t s , and t conv data. table: adc accuracy for vdda = 3.3 v : removed the 4-mhz condition from all parameters. table 47: esd absolute maximum ratings : removed the 4-mhz condition from all parameters; updated footnote 1 and removed footnote 2. table 51: lqfp48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data : added data for t a = 145 c. figure 53 : updated memory size, pin count and package type information. table 55. document revision history (continued) date revision changes docid14395 rev 15 117/125 stm8af526x/8x/ax stm8af6269/8x/ax revision history 124 16-sep-2008 3 replaced the salestype ?stm8h61 xx? with ?stm8ah61xx on the first page. added ?part numbers? to heading rows of table 1: device summary . updated the 80-pin package silhouet te on cover page in line with poa 0062342-revd. table 18 : renamed ?tmu key registers 0-7 [7:0]? as ?tmu key registers 1-8 [7:0]? section 9 : updated introductory text concerning option bytes which do not need to be saved in a complementary form. table 18 : renamed the option bits ?tmu[0:3]?, ?ntmu[0:3]?, and ?tmu_key 0-7 [7:0]? as ?tmu[3:0]?, ?ntmu[3:0] ?, and ?tmu_key 1-8 [7:0]? respectively. table 21 : updated values of option byte 5 (hsecnt[7:0]); inverted the description of option byte 6 (tmu[3:0]); renamed option bytes 8 to 15 ?tmu_key 0-7 [7:0]?, as ?tmu_key 1-8 [7:0]?. updated 80-pin package information in line with poa 0062342-revd in figure 45 and table 53 . 01-jul-2009 4 added ?stm8ah61xx? and ?stm8ah51xx to document header. updated : features on page 1 (memories, timers, operating temperature, adc and i/os). updated table 1: device summary updated kbyte value of program memory in section: introduction changed the first two lines from the top in section: description . updated figure 1: stm8af526x/8x/ax and stm8af6269/8x/ax block diagram updated section 5: product overview in figure 5: lqfp 48-pin pinout , added usart function to pins 10, 11, and 12; added can tx and can rx functions to pins 35 and 36 respectively. section 6: pinouts and pin description : deleted the text below the table 10: legend/abbreviation for the pin description table table 11: stm8af526x/8x/ax and stm8af6269/8x/ax pin description : 68th, 69th pin (lqfp80): replaced x with a dash for pp output and added a table footnote. updated figure 8: register and memory map . table 12: memory model 128k: updated footnote deleted the table: stack and ram partitioning table 17: stm8a interrupt table : updated priorities 13, 15, 17, 20 and 24 and changed table footnote updated section 7: memory and register map updated table: data memory, table: i/o static characteristics, and table 39: nrst pin characteristics . section 10.1.1: minimum and maximum values : added ambient temperature t a = -40 c updated table 20: voltage characteristics . updated table 21: current characteristics . updated table 22: thermal characteristics . updated table 24: general operating conditions . table 55. document revision history (continued) date revision changes revision history stm8af526x/8x/ax stm8af6269/8x/ax 118/125 docid14395 rev 15 01-jul-2009 4 (continued) removed table : total current consumption and timing in halt, fast active halt and slow active halt modes at v dd = 3.3 v. added table 28: oscillator current consumption . added table 29: programming current consumption . updated table 30: typical peripheral cu rrent consumption vdd = 5.0 v updated table 31: hse external clock characteristics . updated table 32: hse oscillator characteristics . table 20: hse oscillator circuit diagram : changed ?consumption control? to ?current control? section : hse oscillator critical gm formula : clarified formula updated table 33: hsi oscillator characteristics . removed ?ram and hardware registers? removed table: ram and hardware registers. updated table 35: flash program memory/data eeprom memory added table 36: flash program memory . added table 37: data memory . updated table 38: i/o static characteristics . updated table 39: nrst pin characteristics . updated table 40: tim 1, 2, 3, and 4 electrical specifications section 10.3.9: spi interface : changed title from ?spi serial peripheral interface?. updated table 41: spi characteristics . figure 40: spi timing diagram in slave mode and with cpha = 0 : changed title and added footnote. figure 41: spi timing diagram in slave mode and with cpha = 1 : changed the title. updated table 43: adc characteristics . updated figure 43: typical application with adc . removed table: adc accuracy for vdda = 3.3 v. updated table 44: adc accuracy for vdda = 5 v . updated table 46: emi data . updated table 48: electrical sensitivities . added text about ecopack in the section 11: package information . figure 48: lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat package outline : deleted footnote. updated figure 60: stm8af526x/8x/ax and stm8af6269/8x/ax ordering information scheme1 . added section 13: stm8 development tools . 22-oct-2009 5 updated table 1: device summary : added stm8af5178, stm8af519a and stm8af619a. table 55. document revision history (continued) date revision changes docid14395 rev 15 119/125 stm8af526x/8x/ax stm8af6269/8x/ax revision history 124 13-apr-2010 6 updated title on cover page. modified cover page header to clarify the part numbers covered by the datasheets. updated footnote on table 1: device summary to add ?p? order codes. changed definition of ?p? order codes. ?q? order codes (fastrom and eeprom) removed. reorganized the content of section 5: product overview . table 11: stm8af526x/8x/ax and stm8af6269/8x/ax pin description updated pd7/tli alternate function, removed caution note for pd6/ linuart_rx, and added note to pa1/oscin. renamed section 7: memory and register map , and merged content with section: register map . updated figure 8: register and memory map . renamed bl_en and nbl_en, bl and nbl, respectively, in table 18: option bytes . updated afr4 definition in table 19: option byte description . added c ext in table 24: general operating conditions , and section 10.3.1: vcap external capacitor . updated t vdd in table 25: operating conditions at power-up/power- down . moved table 30: typical peripheral current consumption vdd = 5.0 v to section : current consumpt ion for on-chip peripherals . removed v esd(mm) from table 47: esd absolute maximum ratings . updated section 12: ordering information to the devices supported by the datasheet. updated section 13: stm8 development tools . 08-jul-2010 7 added stm8af5168 and stm8af518a part number in figure 4 , and stm8af618a in figure 5 . added stm8af52xx, stm8af6269, stm8af628x, and stm8af62ax. updated d temperature range to -40 to 150c. updated number of i/os on cover page. added table 23: oper ating lifetime . restored v esd(mm) from table 47: esd absolute maximum ratings . table 24: general operating conditions : updated v cap information. esl parameter, and range d maximum junction temperature (t j ). added stm8af52xx and stm8af62xx, and footnote in section 12: ordering information . updated section 13: stm8 development tools : added table: product evolution summary , and split the becan time triggered communication mode limitation in two sections . table 55. document revision history (continued) date revision changes revision history stm8af526x/8x/ax stm8af6269/8x/ax 120/125 docid14395 rev 15 30-jan-2011 8 modified references to reference manual, and flash programming manual in the whole document. added reference to aec q100 standard on cover page. renamed timer types as follows: ? auto-reload timer to general purpose timer ? multipurpose timer to advanced control timer ? system timer to basic timer introduced concept of high de nsity flash program memory. updated the number of i/os for devices in 80-, 64-, and 48-pin packages in table: stm8af52xx product line-up with can, table: stm8af62xx product line-up without can, table: stm8af/h/p51xx product line-up with can, and table: stm8af/h/p61xx product line- up without can. added tmu brief description in section 5.4: flash program and data eeprom , updated tmu_maxatt description in table 19: option byte description , and tmu_mawatt reset value in ta ble 18 : optio n bytes . updated clock sources in section 5.5.1: features . added table 4: peripheral clock gating bits (clk_pckenr1) . added calibration using tim3 in section 5.7.2: auto-wakeup counter . added table 8: adc naming and table 9: communication peripheral naming correspondence . updated spi data rate to f master /2 in section 5.9.3: serial peripheral interface (spi) . added reset state in table 10: legend/abbreviation for the pin description table . table: stm8a microcontroller family pin description: modified footnotes related to pd1/swim, corrected wpu input for pe1 and pe2, and renamed timn_ccx and timn_nccx to timn_chx and timn_chxn, respectively. section: register map: removed can register clk_canccr. removed i2c_pecr register. added footnote for px_idr registers in table 13: i/o port hardware register map . updated register reset values for px_idr and pd_cr1 registers. replaced tables describing register maps and reset values for non- volatile memory, global configuration, reset status, tmu, clock controller, interrupt controller, ti mers, communication interfaces, and adc, by t table 14: general hardware register map . added debug module register map renamed fast active halt mode to active-halt mode with regulator on, and slow active halt mode to active-halt mode with regulator off, updated section 5.6: low-power operating modes , and table 27: total current consumption in halt and active-halt modes. general conditions for vdd applied. ta = -40 c to 55 c unless otherwise stated . i dd(fah) and i dd(sah) renamed i dd(ah); t wu(fah) and t wu(sah) renamed t wu(ah) . table 55. document revision history (continued) date revision changes docid14395 rev 15 121/125 stm8af526x/8x/ax stm8af6269/8x/ax revision history 124 30-jan-2011 8 (continued) removed note 1 in table 24: general operating conditions and note 1 below figure 11: fcpumax versus vdd . removed note 3 in table 26: total current consumption in run, wait and slow mode. general conditions for vdd apply, ta = -40 c to 150 c . removed note 2 in table 31: hse external clock characteristics and table 35: flash program memory/data eeprom memory removed note 1 in table 37: data memory . modified t we maximum value in table 36: flash program memory and ta ble 37 : data memory . added t ifp(nrst) and renamed v f(nrst) t ifp in table 39: nrst pin characteristics . added recommendation concerning nrst pin level, and power consumption sensitive applications, above figure 39: recommended reset pin protection , and updated external capacitor value. updated note 1 in table 40: tim 1, 2, 3, and 4 electrical specifications . updated note 1 in table 41: spi characteristics . moved know limitations to separate errata sheet. added ?not recommended for new design? note to device family 51, memory size 7 and 9, and temperature range b, in figure 60: stm8af526x/8x/ax and stm8af6269/8x/ax ordering information scheme1 . added raisonance compiler in section 13.2: software tools . 18-jul-2012 9 updated wildcards of do cument part numbers. added vfqfpn package. added stm8af62a6 part number. table 1: device summary updated footnote 1 and added footnote 2 . table: stm8af52xx product line-up with can and table: stm8af62xx product line-up without can : added ?p? version for all order codes; updated size of data eeprom for 64k devices to 2k instead of 1.5k; updated ram. figure 1: stm8af526x/8x/ax and stm8af6269/8x/ax block diagram : updated por, bor and wd g; removed pdr; added legend. section 5.4: flash program and data eeprom : removed non relevant bullet points and added a sentence about the factory program. added table 4: peripheral clock gating bits (clk_pckenr1) and updated table 5: peripheral clock gating bits (clk_pckenr2) section : adc features : updated adc input range. table 12: memory model 128k : updated ram size, ram end addresses, and stack roll-o ver addresses; updated footnote 1 table 18: option bytes : updated factory default setting for nopt17; updated footnotes. table 20: voltage characteristics : updated v ddx - v dd to v ddx - v ss . table 24: general operating conditions : updated v cap . table 55. document revision history (continued) date revision changes revision history stm8af526x/8x/ax stm8af6269/8x/ax 122/125 docid14395 rev 15 18-jul-2012 9 (continued) table 26: total current consumption in run, wait and slow mode. general conditions for vdd apply, ta = -40 c to 150 c : updated conditions for i dd(run) . table 38: i/o static characteristics : added new condition and new max values for rise and fall time; updated footnote 2 . section 10.3.7: reset pin characteristics : updated text below figure 38: typical nrst pull-up current ipu vs vdd figure 39: recommended reset pin protection : updated unit of capacitor. table 41: spi characteristics : updated sck high and low time conditions and values. figure 42: spi timing diagram - master mode : replaced ?sck input? signals with ?sck output? signals. updated table 49: lqfp80 - 80-pin, 14 x 14 mm low-profile quad flat package mechanical data , table 50: lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data , table 51: lqfp48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data , table 52: lqfp32 - 32-pin, 7 x 7 mm low-profile quad flat package mechanical data , table 53: vfqfpn32 - 32-pin, 5 x 5 mm, 0.5 mm pitch very thin profile fine pitch quad flat package mechanical data replaced figure 48: lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat package outline , figure 51: lqfp48 - 48-pin, 7 x 7 mm low- profile quad flat package outline and figure 54: lqfp32 - 32-pin, 7 x 7 mm low-profile quad flat package outline added figure 49: lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat package recommended footprint , figure 52: lqfp48 - 48-pin, 7 x 7 mm low-profile quad flat package recommended footprint and figure 55: lqfp32 - 32-pin, 7 x 7 mm low-profile quad flat package recommended footprint updated figure 57: vfqfpn32 - 32-pin, 5x5 mm, 0.5 mm pitch very thin profile fine pitch quad flat package outline updated figure 60: stm8af526x/8x/ax and stm8af6269/8x/ax ordering information scheme1 section 13.2.2: c and assembly toolchains : added www.iar.com. 31-mar-2014 10 updated: ? table 1: device summary , ? table: stm8af52xx product line-up with can, ? table: stm8af/h/p51xx product line-up with can, ? table: stm8af/h/p61xx product line-up without can , ? table 11: stm8af526x/8x/ax and stm8af6269/8x/ax pin description , ? the maximum speed in section 5.9.3: serial peripheral interface (spi) , ?t temp reset release delay /vdd rising typical and max values in table 25: operating condition s at power-up/power-down , ? the symbol t ifp(nrst) with t infp(nrst) in table 39: nrst pin characteristics , ? the address and comment for reset in table 17: stm8a interrupt table . table 55. document revision history (continued) date revision changes docid14395 rev 15 123/125 stm8af526x/8x/ax stm8af6269/8x/ax revision history 124 31-mar-2014 10 (continued) added: ? figure 7: stm8af52x6 vfqfpn32 32-pin pinout ; ? the caution in section 5.10: input/ou tput specifications , ? the table footnote ?not recommended for new designs? to table: stm8af/h/p51xx product line-up with can and table: stm8af/h/p61xx product line-up without can. ? the figure footnotes to figure 7: stm8af52x6 vfqfpn32 32-pin pinout and figure: vfqfpn 32-lead very thin fine pitch quad flat no-lead package (5 x 5) 13-jun-2014 11 added stm8af52a6 part number. 09-jun-2015 12 added: ? the third table footnote to table 25: operating conditions at power- up/power-down , ? figure 47: lqfp80 marking example (package top view) , ? figure 50: lqfp64 marking example (package top view) , ? figure 53: lqfp48 marking example (package top view) , ? figure 56: lqfp32 marking example (package top view) , ? figure 59: vfqfpn32 marking example (package top view) , ? the footnote about the device marking to figure 60: stm8af526x/8x/ax and stm8af6269/8x/ax ordering information scheme1 . removed stm8af51xx and stm8af61xx obsolete root part numbers, and consequently ?h? products: ? table 1: device summary , ? section 1: introduction , ? section 2: description , ? section 3: product line-up , ? table 12: memory model 128k , ? section 10.3: operating conditions , ? figure 60: stm8af526x/8x/ax and stm8af6269/8x/ax ordering information scheme1 . moved section 11.6: therma l characteristics to section 11: package information . updated: ? the product naming in the document headers and captions, ? the standard reference for emi characteristics in table 46: emi data . 13-jun-2016 13 updated table 53: vfqfpn32 - 32-pin, 5 x 5 mm, 0.5 mm pitch very thin profile fine pitch quad flat package mechanical data table 55. document revision history (continued) date revision changes revision history stm8af526x/8x/ax stm8af6269/8x/ax 124/125 docid14395 rev 15 13-oct-2016 14 updated: ? title of figure 7: stm8af52x6 vfqfpn32 32-pin pinout , (previously stm8af5286uc vfqfpn32 32-pin pinout) ? footnotes of figure 60: stm8af526x/8x/ax and stm8af6269/8x/ax ordering information scheme1 ? table 11: stm8af526x/8x/ax and stm8af6269/8x/ax pin description replaced ?stm8af5286uc vqfpn32? with ?stm8af52x6 vqfpn32? at header row ? section 10.2: absolu te maximum ratings ? section : device marking on page 93 ? section : device marking on page 96 ? section : device marking on page 99 ? section : device marking on page 104 ? section : device marking on page 108 added: ? footnote on figure 47: lqfp80 marking example (package top view) , figure 50: lqfp64 marking example (package top view) , figure 56: lqfp32 marking example (package top view) , figure 59: vfqfpn32 marking example (package top view) . 10-nov-2016 15 updated header row and pa6/usart_ck pin row on ta ble 11 : stm8af526x/8x/ax and stm8af6269/8x/ax pin description . table 55. document revision history (continued) date revision changes docid14395 rev 15 125/125 stm8af526x/8x/ax stm8af6269/8x/ax 125 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2016 stmicroelectronics ? all rights reserved |
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